Commit a19620ea authored Jan 30, 2020 by Sung Lee Committed by Alex Deucher Mar 19, 2020

drm/amd/display: Program self refresh control register on boot



[WHY]
In headless boot cases, self refresh control registers are not
programmed on boot. In certain hybrid graphics cases this may cause
cstate entering to get blocked causing a hang.

[HOW]
Program self refresh control register on boot.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 201a9446

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -1356,6 +1356,9 @@ void dcn10_init_hw(struct dc *dc)
		*/
		if (dcb->funcs->is_accelerated_mode(dcb) \|\| dc->config.power_down_display_on_boot) {
		hws->funcs.init_pipes(dc, dc->current_state);
		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
		dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
		!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
		}

		for (i = 0; i < res_pool->audio_count; i++) {

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