Commit a18c8e0b authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

clk: meson: g12a: add support for the SPICC SCLK Source clocks 



This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC
controller to provide a more complete range of frequencies instead of the
SPICC internal divider over Xtal.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 51a0c29b

drivers/clk/meson/g12a.c

+129 −0
Original line number Diff line number Diff line
@@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = { 
	},

};



/* SPICC SCLK source clock */



static const struct clk_parent_data spicc_sclk_parent_data[] = {

	{ .fw_name = "xtal", },

	{ .hw = &g12a_clk81.hw },

	{ .hw = &g12a_fclk_div4.hw },

	{ .hw = &g12a_fclk_div3.hw },

	{ .hw = &g12a_fclk_div5.hw },

	{ .hw = &g12a_fclk_div7.hw },

};



static struct clk_regmap g12a_spicc0_sclk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.mask = 7,

		.shift = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = spicc_sclk_parent_data,

		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),

	},

};



static struct clk_regmap g12a_spicc0_sclk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.shift = 0,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc0_sclk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_spicc0_sclk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.bit_idx = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc0_sclk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_spicc1_sclk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.mask = 7,

		.shift = 23,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = spicc_sclk_parent_data,

		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),

	},

};



static struct clk_regmap g12a_spicc1_sclk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.shift = 16,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc1_sclk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_spicc1_sclk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.bit_idx = 22,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc1_sclk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
@@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { 
		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,

		[CLKID_TS_DIV]			= &g12a_ts_div.hw,

		[CLKID_TS]			= &g12a_ts.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { 
		[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,

		[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,

		[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { 
		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,

		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,

		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&sm1_cpu1_clk,

	&sm1_cpu2_clk,

	&sm1_cpu3_clk,

	&g12a_spicc0_sclk_sel,

	&g12a_spicc0_sclk_div,

	&g12a_spicc0_sclk,

	&g12a_spicc1_sclk_sel,

	&g12a_spicc1_sclk_div,

	&g12a_spicc1_sclk,

};



static const struct reg_sequence g12a_init_regs[] = {

drivers/clk/meson/g12a.h

+5 −1
Original line number Diff line number Diff line
@@ -255,8 +255,12 @@ 
#define CLKID_DSU_CLK_DYN1			249

#define CLKID_DSU_CLK_DYN			250

#define CLKID_DSU_CLK_FINAL			251

#define CLKID_SPICC0_SCLK_SEL			256

#define CLKID_SPICC0_SCLK_DIV			257

#define CLKID_SPICC1_SCLK_SEL			259

#define CLKID_SPICC1_SCLK_DIV			260



#define NR_CLKS					256

#define NR_CLKS					262



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/g12a-clkc.h>

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