dt-bindings: display: msm: Convert GMU bindings to YAML

Qualcomm adreno/snapdragon GMU (Graphics management unit)

The GMU is a programmable power controller for the GPU. the CPU controls the

GMU which in turn handles power controls for the GPU.

Required properties:

- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"

    for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"

  Note that you need to list the less specific "qcom,adreno-gmu"

  for generic matches and the more specific identifier to identify

  the specific device.

- reg: Physical base address and length of the GMU registers.

- reg-names: Matching names for the register regions

  * "gmu"

  * "gmu_pdc"

  * "gmu_pdc_seg"

- interrupts: The interrupt signals from the GMU.

- interrupt-names: Matching names for the interrupts

  * "hfi"

  * "gmu"

- clocks: phandles to the device clocks

- clock-names: Matching names for the clocks

   * "gmu"

   * "cxo"

   * "axi"

   * "mnoc"

- power-domains: should be:

	<&clock_gpucc GPU_CX_GDSC>

	<&clock_gpucc GPU_GX_GDSC>

- power-domain-names: Matching names for the power domains

- iommus: phandle to the adreno iommu

- operating-points-v2: phandle to the OPP operating points

Example:

/ {

	...

	gmu: gmu@506a000 {

		compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

		reg = <0x506a000 0x30000>,

			<0xb280000 0x10000>,

			<0xb480000 0x10000>;

		reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hfi", "gmu";

		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

			<&gpucc GPU_CC_CXO_CLK>,

			<&gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&gcc GCC_GPU_MEMNOC_GFX_CLK>;

		clock-names = "gmu", "cxo", "axi", "memnoc";

		power-domains = <&gpucc GPU_CX_GDSC>,

				<&gpucc GPU_GX_GDSC>;

		power-domain-names = "cx", "gx";

		iommus = <&adreno_smmu 5>;

		operating-points-v2 = <&gmu_opp_table>;

	};

};

# SPDX-License-Identifier: GPL-2.0-only

# Copyright 2019-2020, The Linux Foundation, All Rights Reserved

%YAML 1.2

---

$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Devicetree bindings for the GMU attached to certain Adreno GPUs

maintainers:

  - Rob Clark <robdclark@gmail.com>

description: |

  These bindings describe the Graphics Management Unit (GMU) that is attached

  to members of the Adreno A6xx GPU family. The GMU provides on-device power

  management and support to improve power efficiency and reduce the load on

  the CPU.

properties:

  compatible:

    items:

      - enum:

          - qcom,adreno-gmu-630.2

      - const: qcom,adreno-gmu

  reg:

    items:

      - description: Core GMU registers

      - description: GMU PDC registers

      - description: GMU PDC sequence registers

  reg-names:

    items:

      - const: gmu

      - const: gmu_pdc

      - const: gmu_pdc_seq

  clocks:

    items:

     - description: GMU clock

     - description: GPU CX clock

     - description: GPU AXI clock

     - description: GPU MEMNOC clock

  clock-names:

    items:

      - const: gmu

      - const: cxo

      - const: axi

      - const: memnoc

  interrupts:

    items:

     - description: GMU HFI interrupt

     - description: GMU interrupt

  interrupt-names:

    items:

      - const: hfi

      - const: gmu

  power-domains:

     items:

       - description: CX power domain

       - description: GX power domain

  power-domain-names:

     items:

       - const: cx

       - const: gx

  iommus:

    maxItems: 1

  operating-points-v2: true

required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - power-domains

  - power-domain-names

  - iommus

  - operating-points-v2

examples:

 - |

   #include <dt-bindings/clock/qcom,gpucc-sdm845.h>

   #include <dt-bindings/clock/qcom,gcc-sdm845.h>

   #include <dt-bindings/interrupt-controller/irq.h>

   #include <dt-bindings/interrupt-controller/arm-gic.h>

   gmu: gmu@506a000 {

        compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

        reg = <0x506a000 0x30000>,

              <0xb280000 0x10000>,

              <0xb480000 0x10000>;

        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

                 <&gpucc GPU_CC_CXO_CLK>,

                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;

        clock-names = "gmu", "cxo", "axi", "memnoc";

        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "hfi", "gmu";

        power-domains = <&gpucc GPU_CX_GDSC>,

                        <&gpucc GPU_GX_GDSC>;

        power-domain-names = "cx", "gx";

        iommus = <&adreno_smmu 5>;

        operating-points-v2 = <&gmu_opp_table>;

   };