Commit a155b752 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next 

Hope I'm not too late before the cutoff for the v4.11 with these patches.
Mostly an asorted set of fixes that we have discovered while playing with
the code and preparing for the next set of features.

* 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld:
  drm: mali-dp: fix stride setting for multi-plane formats
  drm: mali-dp: Add plane offset to the plane's physical start address register
  drm: mali-dp: Check for sufficient address space
  drm: mali-dp: Check hw version matches device-tree
  drm: mali-dp: Rename malidp_input_format to malidp_pixel_format
  drm: mali-dp: fix Lx_CONTROL register fields clobber
  drm: mali-dp: Fix transposed horizontal/vertical flip
  drm: mali-dp: Fix destination size handling when rotating
  drm: mali-dp: Don't force source size == crtc size
  drm: mali-dp: Check more use cases in the plane's ->atomic_check()
  drm: malidp: Remove event_list member from struct malidp_drm
  drm/arm/malidp: Fix possible dereference of NULL
parents a5b2b6eb 83d642ee

drivers/gpu/drm/arm/malidp_drv.c

+72 −2
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
#include <drm/drm_atomic_helper.h>

#include <drm/drm_crtc.h>

#include <drm/drm_crtc_helper.h>

#include <drm/drm_fb_helper.h>

#include <drm/drm_fb_cma_helper.h>

#include <drm/drm_gem_cma_helper.h>

#include <drm/drm_of.h>
@@ -256,6 +255,60 @@ static const struct of_device_id malidp_drm_of_match[] = { 
};

MODULE_DEVICE_TABLE(of, malidp_drm_of_match);



static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,

				       const struct of_device_id *dev_id)

{

	u32 core_id;

	const char *compatstr_dp500 = "arm,mali-dp500";

	bool is_dp500;

	bool dt_is_dp500;



	/*

	 * The DP500 CORE_ID register is in a different location, so check it

	 * first. If the product id field matches, then this is DP500, otherwise

	 * check the DP550/650 CORE_ID register.

	 */

	core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);

	/* Offset 0x18 will never read 0x500 on products other than DP500. */

	is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);

	dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,

			      sizeof(dev_id->compatible)) != NULL;

	if (is_dp500 != dt_is_dp500) {

		DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",

			  dev_id->compatible, is_dp500 ? "is" : "is not");

		return false;

	} else if (!dt_is_dp500) {

		u16 product_id;

		char buf[32];



		core_id = malidp_hw_read(hwdev,

					 MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);

		product_id = MALIDP_PRODUCT_ID(core_id);

		snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);

		if (!strnstr(dev_id->compatible, buf,

			     sizeof(dev_id->compatible))) {

			DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",

				  dev_id->compatible, product_id);

			return false;

		}

	}

	return true;

}



static bool malidp_has_sufficient_address_space(const struct resource *res,

						const struct of_device_id *dev_id)

{

	resource_size_t res_size = resource_size(res);

	const char *compatstr_dp500 = "arm,mali-dp500";



	if (!strnstr(dev_id->compatible, compatstr_dp500,

		     sizeof(dev_id->compatible)))

		return res_size >= MALIDP550_ADDR_SPACE_SIZE;

	else if (res_size < MALIDP500_ADDR_SPACE_SIZE)

		return false;

	return true;

}



#define MAX_OUTPUT_CHANNELS	3



static int malidp_bind(struct device *dev)
@@ -266,6 +319,7 @@ static int malidp_bind(struct device *dev) 
	struct malidp_drm *malidp;

	struct malidp_hw_device *hwdev;

	struct platform_device *pdev = to_platform_device(dev);

	struct of_device_id const *dev_id;

	/* number of lines for the R, G and B output */

	u8 output_width[MAX_OUTPUT_CHANNELS];

	int ret = 0, i;
@@ -286,7 +340,6 @@ static int malidp_bind(struct device *dev) 
	memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));

	malidp->dev = hwdev;



	INIT_LIST_HEAD(&malidp->event_list);



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	hwdev->regs = devm_ioremap_resource(dev, res);
@@ -329,6 +382,23 @@ static int malidp_bind(struct device *dev) 
	clk_prepare_enable(hwdev->aclk);

	clk_prepare_enable(hwdev->mclk);



	dev_id = of_match_device(malidp_drm_of_match, dev);

	if (!dev_id) {

		ret = -EINVAL;

		goto query_hw_fail;

	}



	if (!malidp_has_sufficient_address_space(res, dev_id)) {

		DRM_ERROR("Insufficient address space in device-tree.\n");

		ret = -EINVAL;

		goto query_hw_fail;

	}



	if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {

		ret = -EINVAL;

		goto query_hw_fail;

	}



	ret = hwdev->query_hw(hwdev);

	if (ret) {

		DRM_ERROR("Invalid HW configuration\n");

drivers/gpu/drm/arm/malidp_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -15,12 +15,12 @@ 


#include <linux/mutex.h>

#include <linux/wait.h>

#include <drm/drmP.h>

#include "malidp_hw.h"



struct malidp_drm {

	struct malidp_hw_device *dev;

	struct drm_fbdev_cma *fbdev;

	struct list_head event_list;

	struct drm_crtc crtc;

	wait_queue_head_t wq;

	atomic_t config_valid;

drivers/gpu/drm/arm/malidp_hw.c

+22 −19
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
#include "malidp_drv.h"

#include "malidp_hw.h"



static const struct malidp_input_format malidp500_de_formats[] = {

static const struct malidp_format_id malidp500_de_formats[] = {

	/*    fourcc,   layers supporting the format,     internal id  */

	{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  0 },

	{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  1 },
@@ -69,21 +69,21 @@ static const struct malidp_input_format malidp500_de_formats[] = { 
	{ DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) },	\

	{ DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }



static const struct malidp_input_format malidp550_de_formats[] = {

static const struct malidp_format_id malidp550_de_formats[] = {

	MALIDP_COMMON_FORMATS,

};



static const struct malidp_layer malidp500_layers[] = {

	{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE },

	{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE },

	{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE },

	{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE, MALIDP_DE_LG_STRIDE },

	{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE, MALIDP_DE_LG_STRIDE },

};



static const struct malidp_layer malidp550_layers[] = {

	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE },

	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE },

	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE },

	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE },

	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE },

	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, 0 },

};



#define MALIDP_DE_DEFAULT_PREFETCH_START	5
@@ -436,8 +436,8 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = { 
				.irq_mask = MALIDP500_DE_IRQ_CONF_VALID,

				.vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,

			},

			.input_formats = malidp500_de_formats,

			.n_input_formats = ARRAY_SIZE(malidp500_de_formats),

			.pixel_formats = malidp500_de_formats,

			.n_pixel_formats = ARRAY_SIZE(malidp500_de_formats),

			.bus_align_bytes = 8,

		},

		.query_hw = malidp500_query_hw,
@@ -447,6 +447,7 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = { 
		.set_config_valid = malidp500_set_config_valid,

		.modeset = malidp500_modeset,

		.rotmem_required = malidp500_rotmem_required,

		.features = MALIDP_DEVICE_LV_HAS_3_STRIDES,

	},

	[MALIDP_550] = {

		.map = {
@@ -469,8 +470,8 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = { 
				.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,

				.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,

			},

			.input_formats = malidp550_de_formats,

			.n_input_formats = ARRAY_SIZE(malidp550_de_formats),

			.pixel_formats = malidp550_de_formats,

			.n_pixel_formats = ARRAY_SIZE(malidp550_de_formats),

			.bus_align_bytes = 8,

		},

		.query_hw = malidp550_query_hw,
@@ -480,6 +481,7 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = { 
		.set_config_valid = malidp550_set_config_valid,

		.modeset = malidp550_modeset,

		.rotmem_required = malidp550_rotmem_required,

		.features = 0,

	},

	[MALIDP_650] = {

		.map = {
@@ -503,8 +505,8 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = { 
				.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,

				.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,

			},

			.input_formats = malidp550_de_formats,

			.n_input_formats = ARRAY_SIZE(malidp550_de_formats),

			.pixel_formats = malidp550_de_formats,

			.n_pixel_formats = ARRAY_SIZE(malidp550_de_formats),

			.bus_align_bytes = 16,

		},

		.query_hw = malidp650_query_hw,
@@ -514,6 +516,7 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = { 
		.set_config_valid = malidp550_set_config_valid,

		.modeset = malidp550_modeset,

		.rotmem_required = malidp550_rotmem_required,

		.features = 0,

	},

};
@@ -522,10 +525,10 @@ u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map, 
{

	unsigned int i;



	for (i = 0; i < map->n_input_formats; i++) {

		if (((map->input_formats[i].layer & layer_id) == layer_id) &&

		    (map->input_formats[i].format == format))

			return map->input_formats[i].id;

	for (i = 0; i < map->n_pixel_formats; i++) {

		if (((map->pixel_formats[i].layer & layer_id) == layer_id) &&

		    (map->pixel_formats[i].format == format))

			return map->pixel_formats[i].id;

	}



	return MALIDP_INVALID_FORMAT_ID;

drivers/gpu/drm/arm/malidp_hw.h

+9 −4
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ enum { 
	DE_SMART = BIT(4),

};



struct malidp_input_format {

struct malidp_format_id {

	u32 format;		/* DRM fourcc */

	u8 layer;		/* bitmask of layers supporting it */

	u8 id;			/* used internally */
@@ -58,6 +58,7 @@ struct malidp_layer { 
	u16 id;			/* layer ID */

	u16 base;		/* address offset for the register bank */

	u16 ptr;		/* address offset for the pointer register */

	u16 stride_offset;	/* Offset to the first stride register. */

};



/* regmap features */
@@ -85,14 +86,18 @@ struct malidp_hw_regmap { 
	const struct malidp_irq_map se_irq_map;

	const struct malidp_irq_map dc_irq_map;



	/* list of supported input formats for each layer */

	const struct malidp_input_format *input_formats;

	const u8 n_input_formats;

	/* list of supported pixel formats for each layer */

	const struct malidp_format_id *pixel_formats;

	const u8 n_pixel_formats;



	/* pitch alignment requirement in bytes */

	const u8 bus_align_bytes;

};



/* device features */

/* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */

#define MALIDP_DEVICE_LV_HAS_3_STRIDES	BIT(0)



struct malidp_hw_device {

	const struct malidp_hw_regmap map;

	void __iomem *regs;

drivers/gpu/drm/arm/malidp_planes.c

+65 −27
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
 */



#include <drm/drmP.h>

#include <drm/drm_atomic.h>

#include <drm/drm_atomic_helper.h>

#include <drm/drm_fb_cma_helper.h>

#include <drm/drm_gem_cma_helper.h>
@@ -36,7 +37,6 @@ 
#define   LAYER_V_VAL(x)		(((x) & 0x1fff) << 16)

#define MALIDP_LAYER_COMP_SIZE		0x010

#define MALIDP_LAYER_OFFSET		0x014

#define MALIDP_LAYER_STRIDE		0x018



/*

 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
@@ -67,13 +67,14 @@ drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane) 
		return NULL;



	state = kmalloc(sizeof(*state), GFP_KERNEL);

	if (state) {

	if (!state)

		return NULL;



	m_state = to_malidp_plane_state(plane->state);

	__drm_atomic_helper_plane_duplicate_state(plane, &state->base);

	state->rotmem_size = m_state->rotmem_size;

	state->format = m_state->format;

	state->n_planes = m_state->n_planes;

	}



	return &state->base;

}
@@ -102,8 +103,10 @@ static int malidp_de_plane_check(struct drm_plane *plane, 
{

	struct malidp_plane *mp = to_malidp_plane(plane);

	struct malidp_plane_state *ms = to_malidp_plane_state(state);

	struct drm_crtc_state *crtc_state;

	struct drm_framebuffer *fb;

	int i;

	struct drm_rect clip = { 0 };

	int i, ret;

	u32 src_w, src_h;



	if (!state->crtc || !state->fb)
@@ -131,8 +134,17 @@ static int malidp_de_plane_check(struct drm_plane *plane, 
	if ((state->crtc_w > mp->hwdev->max_line_size) ||

	    (state->crtc_h > mp->hwdev->max_line_size) ||

	    (state->crtc_w < mp->hwdev->min_line_size) ||

	    (state->crtc_h < mp->hwdev->min_line_size) ||

	    (state->crtc_w != src_w) || (state->crtc_h != src_h))

	    (state->crtc_h < mp->hwdev->min_line_size))

		return -EINVAL;



	/*

	 * DP550/650 video layers can accept 3 plane formats only if

	 * fb->pitches[1] == fb->pitches[2] since they don't have a

	 * third plane stride register.

	 */

	if (ms->n_planes == 3 &&

	    !(mp->hwdev->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&

	    (state->fb->pitches[1] != state->fb->pitches[2]))

		return -EINVAL;



	/* packed RGB888 / BGR888 can't be rotated or flipped */
@@ -141,6 +153,16 @@ static int malidp_de_plane_check(struct drm_plane *plane, 
	     fb->format->format == DRM_FORMAT_BGR888))

		return -EINVAL;



	crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc);

	clip.x2 = crtc_state->adjusted_mode.hdisplay;

	clip.y2 = crtc_state->adjusted_mode.vdisplay;

	ret = drm_plane_helper_check_state(state, &clip,

					   DRM_PLANE_HELPER_NO_SCALING,

					   DRM_PLANE_HELPER_NO_SCALING,

					   true, true);

	if (ret)

		return ret;



	ms->rotmem_size = 0;

	if (state->rotation & MALIDP_ROTATED_MASK) {

		int val;
@@ -157,6 +179,25 @@ static int malidp_de_plane_check(struct drm_plane *plane, 
	return 0;

}



static void malidp_de_set_plane_pitches(struct malidp_plane *mp,

					int num_planes, unsigned int pitches[3])

{

	int i;

	int num_strides = num_planes;



	if (!mp->layer->stride_offset)

		return;



	if (num_planes == 3)

		num_strides = (mp->hwdev->features &

			       MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;



	for (i = 0; i < num_strides; ++i)

		malidp_hw_write(mp->hwdev, pitches[i],

				mp->layer->base +

				mp->layer->stride_offset + i * 4);

}



static void malidp_de_plane_update(struct drm_plane *plane,

				   struct drm_plane_state *old_state)

{
@@ -174,13 +215,8 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
	/* convert src values from Q16 fixed point to integer */

	src_w = plane->state->src_w >> 16;

	src_h = plane->state->src_h >> 16;

	if (plane->state->rotation & MALIDP_ROTATED_MASK) {

		dest_w = plane->state->crtc_h;

		dest_h = plane->state->crtc_w;

	} else {

	dest_w = plane->state->crtc_w;

	dest_h = plane->state->crtc_h;

	}



	malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
@@ -189,11 +225,12 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
		ptr = mp->layer->ptr + (i << 4);



		obj = drm_fb_cma_get_gem_obj(plane->state->fb, i);

		obj->paddr += plane->state->fb->offsets[i];

		malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr);

		malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4);

		malidp_hw_write(mp->hwdev, plane->state->fb->pitches[i],

				mp->layer->base + MALIDP_LAYER_STRIDE);

	}

	malidp_de_set_plane_pitches(mp, ms->n_planes,

				    plane->state->fb->pitches);



	malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),

			mp->layer->base + MALIDP_LAYER_SIZE);
@@ -211,11 +248,12 @@ static void malidp_de_plane_update(struct drm_plane *plane, 


	/* setup the rotation and axis flip bits */

	if (plane->state->rotation & DRM_ROTATE_MASK)

		val = ilog2(plane->state->rotation & DRM_ROTATE_MASK) << LAYER_ROT_OFFSET;

		val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) <<

		       LAYER_ROT_OFFSET;

	if (plane->state->rotation & DRM_REFLECT_X)

		val |= LAYER_V_FLIP;

	if (plane->state->rotation & DRM_REFLECT_Y)

		val |= LAYER_H_FLIP;

	if (plane->state->rotation & DRM_REFLECT_Y)

		val |= LAYER_V_FLIP;



	/*

	 * always enable pixel alpha blending until we have a way to change
@@ -258,7 +296,7 @@ int malidp_de_planes_init(struct drm_device *drm) 
	u32 *formats;

	int ret, i, j, n;



	formats = kcalloc(map->n_input_formats, sizeof(*formats), GFP_KERNEL);

	formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);

	if (!formats) {

		ret = -ENOMEM;

		goto cleanup;
@@ -274,9 +312,9 @@ int malidp_de_planes_init(struct drm_device *drm) 
		}



		/* build the list of DRM supported formats based on the map */

		for (n = 0, j = 0;  j < map->n_input_formats; j++) {

			if ((map->input_formats[j].layer & id) == id)

				formats[n++] = map->input_formats[j].format;

		for (n = 0, j = 0;  j < map->n_pixel_formats; j++) {

			if ((map->pixel_formats[j].layer & id) == id)

				formats[n++] = map->pixel_formats[j].format;

		}



		plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :

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