Commit a1500a62 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: Revert "DP link layer test 4.2.1.1 fix due to specs update" 



[why]
The change causes some regression in a common use case.
Will need more investigation before fixing the original issue.

[how]
This reverts commit fb8cf277.

Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ed8ec123

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+1 −3
Original line number Diff line number Diff line
@@ -690,11 +690,9 @@ static bool detect_dp(struct dc_link *link, 


	if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {

		sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;



		dpcd_set_source_specific_data(link);

		if (!detect_dp_sink_caps(link))

			return false;

		dpcd_set_source_specific_data(link);



		if (is_mst_supported(link)) {

			sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;

			link->type = dc_connection_mst_branch;

drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c

+6 −7
Original line number Diff line number Diff line
@@ -648,17 +648,16 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc, 
}





bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,

uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,

		uint32_t timeout)

{

	bool result = false;

	uint32_t prev_timeout = 0;

	struct ddc *ddc_pin = ddc->ddc_pin;



	if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {

	if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)

		prev_timeout =

				ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);

		result = true;

	}

	return result;

	return prev_timeout;

}



/*test only function*/

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+30 −29
Original line number Diff line number Diff line
@@ -245,7 +245,7 @@ static uint8_t dc_dp_initialize_scrambling_data_symbols( 


static inline bool is_repeater(struct dc_link *link, uint32_t offset)

{

	return (link->lttpr_non_transparent_mode && offset != 0);

	return (!link->is_lttpr_mode_transparent && offset != 0);

}



static void dpcd_set_lt_pattern_and_lane_settings(
@@ -1038,7 +1038,7 @@ static enum link_training_result perform_clock_recovery_sequence( 
		/* 3. wait receiver to lock-on*/

		wait_time_microsec = lt_settings->cr_pattern_time;



		if (link->lttpr_non_transparent_mode)

		if (!link->is_lttpr_mode_transparent)

			wait_time_microsec = TRAINING_AUX_RD_INTERVAL;



		wait_for_training_aux_rd_interval(
@@ -1268,7 +1268,7 @@ static void configure_lttpr_mode(struct dc_link *link) 
		link->dpcd_caps.lttpr_caps.mode = repeater_mode;

	}



	if (link->lttpr_non_transparent_mode) {

	if (!link->is_lttpr_mode_transparent) {



		DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
@@ -1473,7 +1473,7 @@ enum link_training_result dc_link_dp_perform_link_training( 
			&lt_settings);



	/* Configure lttpr mode */

	if (link->lttpr_non_transparent_mode)

	if (!link->is_lttpr_mode_transparent)

		configure_lttpr_mode(link);



	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
@@ -1489,7 +1489,7 @@ enum link_training_result dc_link_dp_perform_link_training( 


	dp_set_fec_ready(link, fec_enable);



	if (link->lttpr_non_transparent_mode) {

	if (!link->is_lttpr_mode_transparent) {



		/* 2. perform link training (set link training done

		 *  to false is done as well)
@@ -1757,7 +1757,7 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link) 
	 * account for lttpr repeaters cap

	 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).

	 */

	if (link->lttpr_non_transparent_mode) {

	if (!link->is_lttpr_mode_transparent) {

		if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)

			max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
@@ -1915,7 +1915,7 @@ bool dp_verify_link_cap( 
	max_link_cap = get_max_link_cap(link);



	/* Grant extended timeout request */

	if (link->lttpr_non_transparent_mode && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {

	if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {

		uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;



		core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
@@ -3248,7 +3248,17 @@ static bool retrieve_link_cap(struct dc_link *link) 
	uint32_t read_dpcd_retry_cnt = 3;

	int i;

	struct dp_sink_hw_fw_revision dp_hw_fw_revision;

	bool is_lttpr_present = false;



	/* Set default timeout to 3.2ms and read LTTPR capabilities */

	bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&

			!link->dc->config.disable_extended_timeout_support;



	link->is_lttpr_mode_transparent = true;



	if (ext_timeout_support) {

		dc_link_aux_configure_timeout(link->ddc,

					LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);

	}



	memset(dpcd_data, '\0', sizeof(dpcd_data));

	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
@@ -3257,13 +3267,6 @@ static bool retrieve_link_cap(struct dc_link *link) 
	memset(&edp_config_cap, '\0',

		sizeof(union edp_configuration_cap));



	/* if extended timeout is supported in hardware,

	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer

	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.

	 */

	dc_link_aux_try_to_configure_timeout(link->ddc,

			LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);



	status = core_link_read_dpcd(link, DP_SET_POWER,

				&dpcd_power_state, sizeof(dpcd_power_state));
@@ -3290,9 +3293,8 @@ static bool retrieve_link_cap(struct dc_link *link) 
		return false;

	}



	if (link->dc->caps.extended_aux_timeout_support) {

		/* By reading LTTPR capability, RX assumes that we will enable LTTPR extended aux timeout if LTTPR is present.

		 * Therefore, only query LTTPR capability when LTTPR extended aux timeout is supported by hardware */

	if (ext_timeout_support) {



		status = core_link_read_dpcd(

				link,

				DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
@@ -3323,20 +3325,19 @@ static bool retrieve_link_cap(struct dc_link *link) 
				lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -

								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];



		is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&

		if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&

				link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&

				link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&

				link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);

		if (is_lttpr_present)

			CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");

				link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) {

			link->is_lttpr_mode_transparent = false;

		} else {

			/*No lttpr reset timeout to its default value*/

			link->is_lttpr_mode_transparent = true;

			dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);

		}



	/* decide lttpr non transparent mode */

	link->lttpr_non_transparent_mode = is_lttpr_present && link->dc->config.allow_lttpr_non_transparent_mode;



	if (!is_lttpr_present)

		dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);



		CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");

	}



	{

		union training_aux_rd_interval aux_rd_interval;

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

+1 −1
Original line number Diff line number Diff line
@@ -281,7 +281,7 @@ void dp_set_hw_lane_settings( 
{

	struct link_encoder *encoder = link->link_enc;



	if (link->lttpr_non_transparent_mode && !is_immediate_downstream(link, offset))

	if (!link->is_lttpr_mode_transparent && !is_immediate_downstream(link, offset))

		return;



	/* call Encoder to set lane settings */

drivers/gpu/drm/amd/display/dc/dc.h

+1 −1
Original line number Diff line number Diff line
@@ -283,7 +283,7 @@ struct dc_config { 
	bool edp_not_connected;

	bool force_enum_edp;

	bool forced_clocks;

	bool allow_lttpr_non_transparent_mode;

	bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well

	bool multi_mon_pp_mclk_switch;

	bool disable_dmcu;

	bool enable_4to1MPC;

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