Commit a13f0655 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v5.2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU updates from Joerg Roedel:

 - ATS support for ARM-SMMU-v3.

 - AUX domain support in the IOMMU-API and the Intel VT-d driver. This
   adds support for multiple DMA address spaces per (PCI-)device. The
   use-case is to multiplex devices between host and KVM guests in a
   more flexible way than supported by SR-IOV.

 - the rest are smaller cleanups and fixes, two of which needed to be
   reverted after testing in linux-next.

* tag 'iommu-updates-v5.2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (45 commits)
  Revert "iommu/amd: Flush not present cache in iommu_map_page"
  Revert "iommu/amd: Remove the leftover of bypass support"
  iommu/vt-d: Fix leak in intel_pasid_alloc_table on error path
  iommu/vt-d: Make kernel parameter igfx_off work with vIOMMU
  iommu/vt-d: Set intel_iommu_gfx_mapped correctly
  iommu/amd: Flush not present cache in iommu_map_page
  iommu/vt-d: Cleanup: no spaces at the start of a line
  iommu/vt-d: Don't request page request irq under dmar_global_lock
  iommu/vt-d: Use struct_size() helper
  iommu/mediatek: Fix leaked of_node references
  iommu/amd: Remove amd_iommu_pd_list
  iommu/arm-smmu: Log CBFRSYNRA register on context fault
  iommu/arm-smmu-v3: Don't disable SMMU in kdump kernel
  iommu/arm-smmu-v3: Disable tagged pointers
  iommu/arm-smmu-v3: Add support for PCI ATS
  iommu/arm-smmu-v3: Link domains and devices
  iommu/arm-smmu-v3: Add a master->domain pointer
  iommu/arm-smmu-v3: Store SteamIDs in master
  iommu/arm-smmu-v3: Rename arm_smmu_master_data to arm_smmu_master
  ACPI/IORT: Check ATS capability in root complex nodes
  ...
parents 55472bae b5531563

drivers/acpi/arm64/iort.c

+11 −0
Original line number Diff line number Diff line
@@ -1031,6 +1031,14 @@ void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *dma_size) 
	dev_dbg(dev, "dma_pfn_offset(%#08llx)\n", offset);

}



static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node)

{

	struct acpi_iort_root_complex *pci_rc;



	pci_rc = (struct acpi_iort_root_complex *)node->node_data;

	return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED;

}



/**

 * iort_iommu_configure - Set-up IOMMU configuration for a device.

 *
@@ -1066,6 +1074,9 @@ const struct iommu_ops *iort_iommu_configure(struct device *dev) 
		info.node = node;

		err = pci_for_each_dma_alias(to_pci_dev(dev),

					     iort_pci_iommu_init, &info);



		if (!err && iort_pci_rc_supports_ats(node))

			dev->iommu_fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS;

	} else {

		int i = 0;

drivers/iommu/Kconfig

+25 −0
Original line number Diff line number Diff line
@@ -359,6 +359,31 @@ config ARM_SMMU 
	  Say Y here if your SoC includes an IOMMU device implementing

	  the ARM SMMU architecture.



config ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT

	bool "Default to disabling bypass on ARM SMMU v1 and v2"

	depends on ARM_SMMU

	default y

	help

	  Say Y here to (by default) disable bypass streams such that

	  incoming transactions from devices that are not attached to

	  an iommu domain will report an abort back to the device and

	  will not be allowed to pass through the SMMU.



	  Any old kernels that existed before this KConfig was

	  introduced would default to _allowing_ bypass (AKA the

	  equivalent of NO for this config).  However the default for

	  this option is YES because the old behavior is insecure.



	  There are few reasons to allow unmatched stream bypass, and

	  even fewer good ones.  If saying YES here breaks your board

	  you should work on fixing your board.  This KConfig option

	  is expected to be removed in the future and we'll simply

	  hardcode the bypass disable in the code.



	  NOTE: the kernel command line parameter

	  'arm-smmu.disable_bypass' will continue to override this

	  config.



config ARM_SMMU_V3

	bool "ARM Ltd. System MMU Version 3 (SMMUv3) Support"

	depends on ARM64

drivers/iommu/amd_iommu.c

+1 −51
Original line number Diff line number Diff line
@@ -1723,31 +1723,6 @@ static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, 
 *

 ****************************************************************************/



/*

 * This function adds a protection domain to the global protection domain list

 */

static void add_domain_to_list(struct protection_domain *domain)

{

	unsigned long flags;



	spin_lock_irqsave(&amd_iommu_pd_lock, flags);

	list_add(&domain->list, &amd_iommu_pd_list);

	spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);

}



/*

 * This function removes a protection domain to the global

 * protection domain list

 */

static void del_domain_from_list(struct protection_domain *domain)

{

	unsigned long flags;



	spin_lock_irqsave(&amd_iommu_pd_lock, flags);

	list_del(&domain->list);

	spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);

}



static u16 domain_id_alloc(void)

{

	int id;
@@ -1838,8 +1813,6 @@ static void dma_ops_domain_free(struct dma_ops_domain *dom) 
	if (!dom)

		return;



	del_domain_from_list(&dom->domain);



	put_iova_domain(&dom->iovad);



	free_pagetable(&dom->domain);
@@ -1880,8 +1853,6 @@ static struct dma_ops_domain *dma_ops_domain_alloc(void) 
	/* Initialize reserved ranges */

	copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);



	add_domain_to_list(&dma_dom->domain);



	return dma_dom;



free_dma_dom:
@@ -2122,23 +2093,6 @@ out_err: 
	return ret;

}



/* FIXME: Move this to PCI code */

#define PCI_PRI_TLP_OFF		(1 << 15)



static bool pci_pri_tlp_required(struct pci_dev *pdev)

{

	u16 status;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return false;



	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);



	return (status & PCI_PRI_TLP_OFF) ? true : false;

}



/*

 * If a device is not yet associated with a domain, this function makes the

 * device visible in the domain
@@ -2167,7 +2121,7 @@ static int attach_device(struct device *dev, 


			dev_data->ats.enabled = true;

			dev_data->ats.qdep    = pci_ats_queue_depth(pdev);

			dev_data->pri_tlp     = pci_pri_tlp_required(pdev);

			dev_data->pri_tlp     = pci_prg_resp_pasid_required(pdev);

		}

	} else if (amd_iommu_iotlb_sup &&

		   pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
@@ -2897,8 +2851,6 @@ static void protection_domain_free(struct protection_domain *domain) 
	if (!domain)

		return;



	del_domain_from_list(domain);



	if (domain->id)

		domain_id_free(domain->id);
@@ -2928,8 +2880,6 @@ static struct protection_domain *protection_domain_alloc(void) 
	if (protection_domain_init(domain))

		goto out_err;



	add_domain_to_list(domain);



	return domain;



out_err:

drivers/iommu/amd_iommu_init.c

+0 −8
Original line number Diff line number Diff line
@@ -188,12 +188,6 @@ static bool amd_iommu_pc_present __read_mostly; 


bool amd_iommu_force_isolation __read_mostly;



/*

 * List of protection domains - used during resume

 */

LIST_HEAD(amd_iommu_pd_list);

spinlock_t amd_iommu_pd_lock;



/*

 * Pointer to the device table which is shared by all AMD IOMMUs

 * it is indexed by the PCI device id or the HT unit id and contains
@@ -2526,8 +2520,6 @@ static int __init early_amd_iommu_init(void) 
	 */

	__set_bit(0, amd_iommu_pd_alloc_bitmap);



	spin_lock_init(&amd_iommu_pd_lock);



	/*

	 * now the data structures are allocated and basically initialized

	 * start the real acpi table scan

drivers/iommu/amd_iommu_types.h

+0 −6
Original line number Diff line number Diff line
@@ -674,12 +674,6 @@ extern struct list_head amd_iommu_list; 
 */

extern struct amd_iommu *amd_iommus[MAX_IOMMUS];



/*

 * Declarations for the global list of all protection domains

 */

extern spinlock_t amd_iommu_pd_lock;

extern struct list_head amd_iommu_pd_list;



/*

 * Structure defining one entry in the device table

 */

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