Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

* Cavium Interrupt Bus widget

Properties:

- compatible: "cavium,octeon-7130-cib"

  Compatibility with cn70XX SoCs.

- interrupt-controller:  This is an interrupt controller.

- reg: Two elements consisting of the addresses of the RAW and EN

  registers of the CIB block

- cavium,max-bits: The index (zero based) of the highest numbered bit

  in the CIB block.

- interrupt-parent:  Always the CIU on the SoC.

- interrupts: The CIU line to which the CIB block is connected.

- #interrupt-cells: Must be <2>.  The first cell is the bit within the

   CIB.  The second cell specifies the triggering semantics of the

   line.

Example:

	interrupt-controller@107000000e000 {

		compatible = "cavium,octeon-7130-cib";

		reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */

		      <0x10700 0x0000e100 0x0 0x8>; /* EN */

		cavium,max-bits = <23>;

		interrupt-controller;

		interrupt-parent = <&ciu>;

		interrupts = <1 24>;

		/* Interrupts are specified by two parts:

		 * 1) Bit number in the CIB* registers

		 * 2) Triggering (1 - edge rising

		 *		  2 - edge falling

		 *		  4 - level active high

		 *		  8 - level active low)

		 */

		#interrupt-cells = <2>;

	};

	select CPU_PM if CPU_IDLE

	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST

	select ARCH_BINFMT_ELF_STATE

	select SYSCTL_EXCEPTION_TRACE

menu "Machine selection"

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_HAS_CPU_MIPS32_R3_5

	select SYS_HAS_CPU_MIPS32_R6

	select SYS_HAS_CPU_MIPS64_R1

	select SYS_HAS_CPU_MIPS64_R2

	select SYS_HAS_CPU_MIPS64_R6

	select SYS_HAS_CPU_NEVADA

	select SYS_HAS_CPU_RM7000

	select SYS_SUPPORTS_32BIT_KERNEL

config NO_IOPORT_MAP

	def_bool n

config GENERIC_CSUM

	bool

config GENERIC_ISA_DMA

	bool

	select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n

	bool

	select SOC_PNX833X

config MIPS_SPRAM

	bool

config SWAP_IO_SPACE

	bool

	  specific type of processor in your system, choose those that one

	  otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.

config CPU_MIPS32_R6

	bool "MIPS32 Release 6 (EXPERIMENTAL)"

	depends on SYS_HAS_CPU_MIPS32_R6

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select GENERIC_CSUM

	select HAVE_KVM

	select MIPS_O32_FP64_SUPPORT

	help

	  Choose this option to build a kernel for release 6 or later of the

	  MIPS32 architecture.  New MIPS processors, starting with the Warrior

	  family, are based on a MIPS32r6 processor. If you own an older

	  processor, you probably need to select MIPS32r1 or MIPS32r2 instead.

config CPU_MIPS64_R1

	bool "MIPS64 Release 1"

	depends on SYS_HAS_CPU_MIPS64_R1

	  specific type of processor in your system, choose those that one

	  otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.

config CPU_MIPS64_R6

	bool "MIPS64 Release 6 (EXPERIMENTAL)"

	depends on SYS_HAS_CPU_MIPS64_R6

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select GENERIC_CSUM

	help

	  Choose this option to build a kernel for release 6 or later of the

	  MIPS64 architecture.  New MIPS processors, starting with the Warrior

	  family, are based on a MIPS64r6 processor. If you own an older

	  processor, you probably need to select MIPS64r1 or MIPS64r2 instead.

config CPU_R3000

	bool "R3000"

	depends on SYS_HAS_CPU_R3000

config CPU_MIPS32_3_5_FEATURES

	bool "MIPS32 Release 3.5 Features"

	depends on SYS_HAS_CPU_MIPS32_R3_5

	depends on CPU_MIPS32_R2

	depends on CPU_MIPS32_R2 || CPU_MIPS32_R6

	help

	  Choose this option to build a kernel for release 2 or later of the

	  MIPS32 architecture including features from the 3.5 release such as

config SYS_HAS_CPU_MIPS32_R3_5

	bool

config SYS_HAS_CPU_MIPS32_R6

	bool

config SYS_HAS_CPU_MIPS64_R1

	bool

config SYS_HAS_CPU_MIPS64_R2

	bool

config SYS_HAS_CPU_MIPS64_R6

	bool

config SYS_HAS_CPU_R3000

	bool

#

config CPU_MIPS32

	bool

	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2

	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6

config CPU_MIPS64

	bool

	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2

	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6

#

# These two indicate the revision of the architecture, either Release 1 or Release 2

config CPU_MIPSR2

	bool

	default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON

	select MIPS_SPRAM

config CPU_MIPSR6

	bool

	default y if CPU_MIPS32_R6 || CPU_MIPS64_R6

	select MIPS_SPRAM

config EVA

	bool

	default y

	depends on MIPS_MT_SMP

config MIPSR2_TO_R6_EMULATOR

	bool "MIPS R2-to-R6 emulator"

	depends on CPU_MIPSR6 && !SMP

	default y

	help

	  Choose this option if you want to run non-R6 MIPS userland code.

	  Even if you say 'Y' here, the emulator will still be disabled by

	  default. You can enable it using the 'mipsr2emul' kernel option.

	  The only reason this is a build-time option is to save ~14K from the

	  final kernel image.

comment "MIPS R2-to-R6 emulator is only available for UP kernels"

	depends on SMP && CPU_MIPSR6

config MIPS_VPE_LOADER

	bool "VPE loader support."

	depends on SYS_SUPPORTS_MULTITHREADING && MODULES

	  here.

config CPU_MICROMIPS

	depends on 32BIT && SYS_SUPPORTS_MICROMIPS

	depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6

	bool "microMIPS"

	help

	  When this option is enabled the kernel will be built using the

	help

	  Add several files to the debugfs to test spinlock speed.

config FP32XX_HYBRID_FPRS

	bool "Run FP32 & FPXX code with hybrid FPRs"

	depends on MIPS_O32_FP64_SUPPORT

	help

	  The hybrid FPR scheme is normally used only when a program needs to

	  execute a mix of FP32 & FP64A code, since the trapping & emulation

	  that it entails is expensive. When enabled, this option will lead

	  to the kernel running programs which use the FP32 & FPXX FP ABIs

	  using the hybrid FPR scheme, which can be useful for debugging

	  purposes.

	  If unsure, say N.

endmenu

cflags-$(CONFIG_CPU_BIG_ENDIAN)		+= $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))

cflags-$(CONFIG_CPU_LITTLE_ENDIAN)	+= $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))

# For smartmips configurations, there are hundreds of warnings due to ISA overrides

# in assembly and header files. smartmips is only supported for MIPS32r1 onwards

# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or

# similar directives in the kernel will spam the build logs with the following warnings:

# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater

# or

# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension

# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has

# been fixed properly.

cflags-$(CONFIG_CPU_HAS_SMARTMIPS)	+= $(call cc-option,-msmartmips) -Wa,--no-warn

cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)

cflags-$(CONFIG_SB1XXX_CORELIS)	+= $(call cc-option,-mno-sched-prolog) \

				   -fno-omit-frame-pointer

ifeq ($(CONFIG_CPU_HAS_MSA),y)

toolchain-msa	:= $(call cc-option-yn,-mhard-float -mfp64 -Wa$(comma)-mmsa)

cflags-$(toolchain-msa)		+= -DTOOLCHAIN_SUPPORTS_MSA

endif

#

# CPU-dependent compiler/assembler options for optimization.

#

			-Wa,-mips32 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R2)	+= $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \

			-Wa,-mips32r2 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R6)	+= -march=mips32r6 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS64_R1)	+= $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \

			-Wa,-mips64 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS64_R2)	+= $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \

			-Wa,-mips64r2 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS64_R6)	+= -march=mips64r6 -Wa,--trap

cflags-$(CONFIG_CPU_R5000)	+= -march=r5000 -Wa,--trap

cflags-$(CONFIG_CPU_R5432)	+= $(call cc-option,-march=r5400,-march=r5000) \

			-Wa,--trap

endif

cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1

cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap

#

# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a

# as MIPS64 R1; older versions as just R1.  This leaves the possibility open

# that GCC might generate R2 code for -march=loongson3a which then is rejected

# by GAS.  The cc-option can't probe for this behaviour so -march=loongson3a

# can't easily be used safely within the kbuild framework.

#

cflags-$(CONFIG_CPU_LOONGSON3)  +=					\

	$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \

	-Wa,-mips64r2 -Wa,--trap

cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)

cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)

endif

endif

# For smartmips configurations, there are hundreds of warnings due to ISA overrides

# in assembly and header files. smartmips is only supported for MIPS32r1 onwards

# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or

# similar directives in the kernel will spam the build logs with the following warnings:

# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater

# or

# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension

# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has

# been fixed properly.

mips-cflags				:= "$(cflags-y)"

cflags-$(CONFIG_CPU_HAS_SMARTMIPS)	+= $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn

cflags-$(CONFIG_CPU_MICROMIPS)		+= $(call cc-option,$(mips-cflags),-mmicromips)

ifeq ($(CONFIG_CPU_HAS_MSA),y)

toolchain-msa				:= $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa)

cflags-$(toolchain-msa)			+= -DTOOLCHAIN_SUPPORTS_MSA

endif

#

# Firmware support

#

boot-y			+= vmlinux.srec

ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)

boot-y			+= uImage

boot-y			+= uImage.bin

boot-y			+= uImage.bz2

boot-y			+= uImage.gz

boot-y			+= uImage.lzma

boot-y			+= uImage.lzo

endif

# compressed boot image targets (arch/mips/boot/compressed/)

	echo '  vmlinuz.bin          - Raw binary zboot image'

	echo '  vmlinuz.srec         - SREC zboot image'

	echo '  uImage               - U-Boot image'

	echo '  uImage.bin           - U-Boot image (uncompressed)'

	echo '  uImage.bz2           - U-Boot image (bz2)'

	echo '  uImage.gz            - U-Boot image (gzip)'

	echo '  uImage.lzma          - U-Boot image (lzma)'

	echo '  uImage.lzo           - U-Boot image (lzo)'

	echo '  dtbs                 - Device-tree blobs for enabled boards'

	echo

	echo '  These will be default as appropriate for a configured platform.'

		t = 396000000;

	else {

		t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;

		if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)

			t &= 0x3f;

		t *= parent_rate;

	}

	return t;

}

void __init alchemy_set_lpj(void)

{

	preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);

	preset_lpj /= 2 * HZ;

}

static struct clk_ops alchemy_clkops_cpu = {

	.recalc_rate	= alchemy_clk_cpu_recalc,

};

/* lrclk: external synchronous static bus clock ***********************/

static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)

static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)

{

	/* MEM_STCFG0[15:13] = divisor.

	/* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,

	 * otherwise lrclk=pclk/4.

	 * All other variants: MEM_STCFG0[15:13] = divisor.

	 * L/RCLK = periph_clk / (divisor + 1)

	 * On Au1000, Au1500, Au1100 it's called LCLK,

	 * on later models it's called RCLK, but it's the same thing.

	 */

	struct clk *c;

	unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;

	unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);

	v = (v & 7) + 1;

	switch (t) {

	case ALCHEMY_CPU_AU1000:

	case ALCHEMY_CPU_AU1500:

		v = 4 + ((v >> 11) & 1);

		break;

	default:	/* all other models */

		v = ((v >> 13) & 7) + 1;

	}

	c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,

				      pn, 0, 1, v);

	if (!IS_ERR(c))

	ERRCK(c)

	/* L/RCLK: external static bus clock for synchronous mode */

	c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);

	c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);

	ERRCK(c)

	/* Frequency dividers 0-5 */