Commit a11b5abe authored by Yinghai Lu's avatar Yinghai Lu Committed by Ingo Molnar
Browse files

x2apic: fix reserved APIC register accesses in print_local_APIC() 



APIC_ARBPRI is a reserved register for XAPIC and beyond.
APIC_RRR is a reserved register except for 82489DX, APIC for Pentium processors.
APIC_EOI is a write only register.
APIC_DFR is reserved in x2apic mode.

Access to these registers in x2apic will result in #GP fault. Fix these
apic register accesses.

Signed-off-by: default avatarYinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent c59d85a7

arch/x86/kernel/io_apic.c

+18 −9
Original line number Diff line number Diff line
@@ -1751,21 +1751,30 @@ __apicdebuginit(void) print_local_APIC(void *dummy) 
	printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);



	if (APIC_INTEGRATED(ver)) {                     /* !82489DX */

		if (!APIC_XAPIC(ver)) {

			v = apic_read(APIC_ARBPRI);

			printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,

			       v & APIC_ARBPRI_MASK);

		}

		v = apic_read(APIC_PROCPRI);

		printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);

	}



	v = apic_read(APIC_EOI);

	printk(KERN_DEBUG "... APIC EOI: %08x\n", v);

	/*

	 * Remote read supported only in the 82489DX and local APIC for

	 * Pentium processors.

	 */

	if (!APIC_INTEGRATED(ver) || maxlvt == 3) {

		v = apic_read(APIC_RRR);

		printk(KERN_DEBUG "... APIC RRR: %08x\n", v);

	}



	v = apic_read(APIC_LDR);

	printk(KERN_DEBUG "... APIC LDR: %08x\n", v);

	if (!x2apic_enabled()) {

		v = apic_read(APIC_DFR);

		printk(KERN_DEBUG "... APIC DFR: %08x\n", v);

	}

	v = apic_read(APIC_SPIV);

	printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);

include/asm-x86/apic.h

+14 −0
Original line number Diff line number Diff line
@@ -98,6 +98,20 @@ extern void check_x2apic(void); 
extern void enable_x2apic(void);

extern void enable_IR_x2apic(void);

extern void x2apic_icr_write(u32 low, u32 id);

static inline int x2apic_enabled(void)

{

	int msr, msr2;



	if (!cpu_has_x2apic)

		return 0;



	rdmsr(MSR_IA32_APICBASE, msr, msr2);

	if (msr & X2APIC_ENABLE)

		return 1;

	return 0;

}

#else

#define x2apic_enabled()	0

#endif



struct apic_ops {

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