Commit a10220bb authored by Martin Peres's avatar Martin Peres Committed by Ben Skeggs
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drm/nouveau/pbus: add a PBUS subdev that hands IRQs to the right subdevs 



We are going to use PTHERM's IRQs for thermal monitoring but we need to route
them first.

On nv31-50, PBUS's IRQ line is shared with GPIOs IRQs.

It seems like nv10-31 GPIO interruptions aren't well handled. I kept the
original behaviour but it is wrong and may lead to an IRQ storm.

Since we enable all PBUS IRQs, we need a way to avoid being stormed if we
don't handle them. The solution I used was to mask the IRQs that have not been
handled. This will also print one message in the logs to let us know.

v2: drop the shared intr handler because of was racy
v3: style fixes
v4: drop a useless construct in the chipset-dependent INTR
v5: add BUS to the disable mask
v6 (Ben Skeggs):
- general tidy to match the rest of the driver's style
- nva3->nvc0, nva3 can be serviced just fine with nv50.c, rnndb even notes
  that the THERM_ALARM bit got left in the hw until fermi anyway.. so, it's
  not going to conflict
- removed the peephole and user stuff, for the moment.. will handle them
  later if we find a good reason to actually care..
- limited INTR_EN to just what we can handle for now, mostly to prevent
  spam of unknown status bits (seen on at least nv4x)

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarMartin Peres <martin.peres@labri.fr>
parent 694472f4

drivers/gpu/drm/nouveau/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ nouveau-y += core/subdev/bios/mxm.o 
nouveau-y += core/subdev/bios/perf.o

nouveau-y += core/subdev/bios/pll.o

nouveau-y += core/subdev/bios/therm.o

nouveau-y += core/subdev/bus/nv04.o

nouveau-y += core/subdev/bus/nv31.o

nouveau-y += core/subdev/bus/nv50.o

nouveau-y += core/subdev/bus/nvc0.o

nouveau-y += core/subdev/clock/nv04.o

nouveau-y += core/subdev/clock/nv40.o

nouveau-y += core/subdev/clock/nv50.o

drivers/gpu/drm/nouveau/core/include/core/device.h

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ enum nv_subdev_type { 
	 */

	NVDEV_SUBDEV_MXM,

	NVDEV_SUBDEV_MC,

	NVDEV_SUBDEV_BUS,

	NVDEV_SUBDEV_TIMER,

	NVDEV_SUBDEV_FB,

	NVDEV_SUBDEV_LTCG,

drivers/gpu/drm/nouveau/core/include/subdev/bus.h

0 → 100644
+41 −0
Original line number Diff line number Diff line 
#ifndef __NOUVEAU_BUS_H__

#define __NOUVEAU_BUS_H__



#include <core/subdev.h>

#include <core/device.h>



struct nouveau_bus_intr {

	u32 stat;

	u32 unit;

};



struct nouveau_bus {

	struct nouveau_subdev base;

};



static inline struct nouveau_bus *

nouveau_bus(void *obj)

{

	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BUS];

}



#define nouveau_bus_create(p, e, o, d)                                         \

	nouveau_subdev_create_((p), (e), (o), 0, "PBUS", "master",             \

			       sizeof(**d), (void **)d)

#define nouveau_bus_destroy(p)                                                 \

	nouveau_subdev_destroy(&(p)->base)

#define nouveau_bus_init(p)                                                    \

	nouveau_subdev_init(&(p)->base)

#define nouveau_bus_fini(p, s)                                                 \

	nouveau_subdev_fini(&(p)->base, (s))



#define _nouveau_bus_dtor _nouveau_subdev_dtor

#define _nouveau_bus_init _nouveau_subdev_init

#define _nouveau_bus_fini _nouveau_subdev_fini



extern struct nouveau_oclass nv04_bus_oclass;

extern struct nouveau_oclass nv31_bus_oclass;

extern struct nouveau_oclass nv50_bus_oclass;

extern struct nouveau_oclass nvc0_bus_oclass;



#endif

drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c

0 → 100644
+95 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Nouveau Community

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Martin Peres <martin.peres@labri.fr>

 *          Ben Skeggs

 */



#include <subdev/bus.h>



struct nv04_bus_priv {

	struct nouveau_bus base;

};



void

nv04_bus_intr(struct nouveau_subdev *subdev)

{

	struct nouveau_bus *pbus = nouveau_bus(subdev);

	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);



	if (stat & 0x00000001) {

		nv_error(pbus, "BUS ERROR\n");

		stat &= ~0x00000001;

		nv_wr32(pbus, 0x001100, 0x00000001);

	}



	if (stat & 0x00000110) {

		subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO);

		if (subdev && subdev->intr)

			subdev->intr(subdev);

		stat &= ~0x00000110;

		nv_wr32(pbus, 0x001100, 0x00000110);

	}



	if (stat) {

		nv_error(pbus, "unknown intr 0x%08x\n", stat);

		nv_mask(pbus, 0x001140, stat, 0x00000000);

	}

}



static int

nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	      struct nouveau_oclass *oclass, void *data, u32 size,

	      struct nouveau_object **pobject)

{

	struct nv04_bus_priv *priv;

	int ret;



	ret = nouveau_bus_create(parent, engine, oclass, &priv);

	*pobject = nv_object(priv);

	if (ret)

		return ret;



	nv_subdev(priv)->intr = nv04_bus_intr;

	return 0;

}



static int

nv04_bus_init(struct nouveau_object *object)

{

	struct nv04_bus_priv *priv = (void *)object;



	nv_wr32(priv, 0x001100, 0xffffffff);

	nv_wr32(priv, 0x001140, 0x00000111);



	return nouveau_bus_init(&priv->base);

}



struct nouveau_oclass

nv04_bus_oclass = {

	.handle = NV_SUBDEV(BUS, 0x04),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nv04_bus_ctor,

		.dtor = _nouveau_bus_dtor,

		.init = nv04_bus_init,

		.fini = _nouveau_bus_fini,

	},

};

drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c

0 → 100644
+106 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Nouveau Community

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Martin Peres <martin.peres@labri.fr>

 *          Ben Skeggs

 */



#include <subdev/bus.h>



struct nv31_bus_priv {

	struct nouveau_bus base;

};



static void

nv31_bus_intr(struct nouveau_subdev *subdev)

{

	struct nouveau_bus *pbus = nouveau_bus(subdev);

	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);

	u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);



	if (gpio) {

		subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO);

		if (subdev && subdev->intr)

			subdev->intr(subdev);

	}



	if (stat & 0x00000008) {

		nv_error(pbus, "MMIO FAULT\n"); /* NV41- */

		stat &= ~0x00000008;

		nv_wr32(pbus, 0x001100, 0x00000008);

	}



	if (stat & 0x00070000) {

		subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);

		if (subdev && subdev->intr)

			subdev->intr(subdev);

		stat &= ~0x00070000;

		nv_wr32(pbus, 0x001100, 0x00070000);

	}



	if (stat) {

		nv_error(pbus, "unknown intr 0x%08x\n", stat);

		nv_mask(pbus, 0x001140, stat, 0x00000000);

	}

}



static int

nv31_bus_init(struct nouveau_object *object)

{

	struct nv31_bus_priv *priv = (void *)object;

	int ret;



	ret = nouveau_bus_init(&priv->base);

	if (ret)

		return ret;



	nv_wr32(priv, 0x001100, 0xffffffff);

	nv_wr32(priv, 0x001140, 0x00070008);

	return 0;

}



static int

nv31_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	      struct nouveau_oclass *oclass, void *data, u32 size,

	      struct nouveau_object **pobject)

{

	struct nv31_bus_priv *priv;

	int ret;



	ret = nouveau_bus_create(parent, engine, oclass, &priv);

	*pobject = nv_object(priv);

	if (ret)

		return ret;



	nv_subdev(priv)->intr = nv31_bus_intr;

	return 0;

}



struct nouveau_oclass

nv31_bus_oclass = {

	.handle = NV_SUBDEV(BUS, 0x31),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nv31_bus_ctor,

		.dtor = _nouveau_bus_dtor,

		.init = nv31_bus_init,

		.fini = _nouveau_bus_fini,

	},

};

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