Commit a0be4737 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'amlogic-dt' of... 

Merge tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

ARM: dts: Amlogic updates for v5.6
- add DDR clock controller
- GPU OPP updates

* tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM: dts: meson8b: use the actual frequency for the GPU's 364MHz OPP
  ARM: dts: meson8: use the actual frequency for the GPU's 182.1MHz OPP
  ARM: dts: meson8b: fix the clock controller compatible string
  ARM: dts: meson8b: add the DDR clock controller
  ARM: dts: meson8: add the DDR clock controller
  ARM: dts: meson: provide the XTAL clock using a fixed-clock
  dt-bindings: clock: meson8b: add the clock inputs
  dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding

Link: https://lore.kernel.org/r/7hwo9udi7m.fsf@baylibre.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 5a74e85a c3dd3315

Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml

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+50 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic DDR Clock Controller Device Tree Bindings



maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>



properties:

  compatible:

    enum:

      - amlogic,meson8-ddr-clkc

      - amlogic,meson8b-ddr-clkc



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: xtal



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    ddr_clkc: clock-controller@400 {

      compatible = "amlogic,meson8-ddr-clkc";

      reg = <0x400 0x20>;

      clocks = <&xtal>;

      clock-names = "xtal";

      #clock-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

+5 −0
Original line number Diff line number Diff line
@@ -11,6 +11,11 @@ Required Properties: 
	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

- #clock-cells: should be 1.

- #reset-cells: should be 1.

- clocks: list of clock phandles, one for each entry in clock-names

- clock-names: should contain the following:

  * "xtal": the 24MHz system oscillator

  * "ddr_pll": the DDR PLL clock

  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)



Parent node should have the following properties :

- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

arch/arm/boot/dts/meson.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -282,4 +282,11 @@ 
			};

		};

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};

}; /* end of / */

arch/arm/boot/dts/meson6.dtsi

+0 −7
Original line number Diff line number Diff line
@@ -36,13 +36,6 @@ 
		ranges = <0x0 0xd0000000 0x40000>;

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};



	clk81: clk@0 {

		#clock-cells = <0>;

		compatible = "fixed-clock";

arch/arm/boot/dts/meson8.dtsi

+19 −9
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * Copyright 2014 Carlo Caione <carlo@caione.org>

 */



#include <dt-bindings/clock/meson8-ddr-clkc.h>

#include <dt-bindings/clock/meson8b-clkc.h>

#include <dt-bindings/gpio/meson8-gpio.h>

#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -129,8 +130,8 @@ 
	gpu_opp_table: gpu-opp-table {

		compatible = "operating-points-v2";



		opp-182150000 {

			opp-hz = /bits/ 64 <182150000>;

		opp-182142857 {

			opp-hz = /bits/ 64 <182142857>;

			opp-microvolt = <1150000>;

		};

		opp-318750000 {
@@ -195,6 +196,14 @@ 
		#size-cells = <1>;

		ranges = <0x0 0xc8000000 0x8000>;



		ddr_clkc: clock-controller@400 {

			compatible = "amlogic,meson8-ddr-clkc";

			reg = <0x400 0x20>;

			clocks = <&xtal>;

			clock-names = "xtal";

			#clock-cells = <1>;

		};



		dmcbus: bus@6000 {

			compatible = "simple-bus";

			reg = <0x6000 0x400>;
@@ -455,6 +464,8 @@ 
&hhi {

	clkc: clock-controller {

		compatible = "amlogic,meson8-clkc";

		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;

		clock-names = "xtal", "ddr_pll";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -529,8 +540,7 @@ 


&saradc {

	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";

	clocks = <&clkc CLKID_XTAL>,

		<&clkc CLKID_SAR_ADC>;

	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;

	clock-names = "clkin", "core";

	amlogic,hhi-sysctrl = <&hhi>;

	nvmem-cells = <&temperature_calib>;
@@ -548,31 +558,31 @@ 
};



&timer_abcde {

	clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

	clocks = <&xtal>, <&clkc CLKID_CLK81>;

	clock-names = "xtal", "pclk";

};



&uart_AO {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;

	clock-names = "baud", "xtal", "pclk";

};



&uart_A {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;

	clock-names = "baud", "xtal", "pclk";

};



&uart_B {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;

	clock-names = "baud", "xtal", "pclk";

};



&uart_C {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;

	clock-names = "baud", "xtal", "pclk";

};

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