Commit a0bcd3c0 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Borislav Petkov
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EDAC/mce_amd: Decode MCA_STATUS in bit definition order 



Sort the MCA_STATUS bits in decode output to follow how they are defined
in the register.

The order is as follows:

  Bit | Decode
  ------------
  62  | Over
  61  | UC
  59  | MiscV
  58  | AddrV
  57  | PCC
  55  | TCC
  53  | SyndV
  46  | CECC
  45  | UECC
  44  | Deferred
  43  | Poison
  40  | Scrub

 [ bp: Massage a bit. ]

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86@kernel.org
Link: https://lkml.kernel.org/r/20190212212417.107049-2-Yazen.Ghannam@amd.com
parent 3f4da372

drivers/edac/mce_amd.c

+12 −12
Original line number Original line Diff line number Diff line
@@ -1051,26 +1051,18 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) 
		((m->status & MCI_STATUS_UC)	? "UE"	  :

		((m->status & MCI_STATUS_UC)	? "UE"	  :

		 (m->status & MCI_STATUS_DEFERRED) ? "-"  : "CE"),

		 (m->status & MCI_STATUS_DEFERRED) ? "-"  : "CE"),

		((m->status & MCI_STATUS_MISCV)	? "MiscV" : "-"),

		((m->status & MCI_STATUS_MISCV)	? "MiscV" : "-"),

		((m->status & MCI_STATUS_PCC)	? "PCC"	  : "-"),

		((m->status & MCI_STATUS_ADDRV)	? "AddrV" : "-"),

		((m->status & MCI_STATUS_ADDRV)	? "AddrV" : "-"));

		((m->status & MCI_STATUS_PCC)	? "PCC"	  : "-"));



	if (fam >= 0x15) {

		pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));



		/* F15h, bank4, bit 43 is part of McaStatSubCache. */

		if (fam != 0x15 || m->bank != 4)

			pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));

	}





	if (boot_cpu_has(X86_FEATURE_SMCA)) {

	if (boot_cpu_has(X86_FEATURE_SMCA)) {

		u32 low, high;

		u32 low, high;

		u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);

		u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);





		pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));



		if (!rdmsr_safe(addr, &low, &high) &&

		if (!rdmsr_safe(addr, &low, &high) &&

		    (low & MCI_CONFIG_MCAX))

		    (low & MCI_CONFIG_MCAX))

			pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));

			pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));



		pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));

	}

	}





	/* do the two bits[14:13] together */

	/* do the two bits[14:13] together */
@@ -1078,6 +1070,14 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) 
	if (ecc)

	if (ecc)

		pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));

		pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));





	if (fam >= 0x15) {

		pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));



		/* F15h, bank4, bit 43 is part of McaStatSubCache. */

		if (fam != 0x15 || m->bank != 4)

			pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));

	}



	if (fam >= 0x17)

	if (fam >= 0x17)

		pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));

		pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));

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