Commit a0b1910e authored Mar 25, 2017 by Icenowy Zheng Committed by Kishon Vijay Abraham I Apr 10, 2017

dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64



Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.

When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.

Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

parent 0ccf7d87

Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -15,6 +15,7 @@ Required properties:
		- reg : a list of offset + length pairs
		- reg-names :
		* "phy_ctrl"
		* "pmu0" for H3, V3s and A64
		* "pmu1"
		* "pmu2" for sun4i, sun6i or sun7i
		- #phy-cells : from the generic phy bindings, must be 1

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