x86: Introduce and use MP IRQ trigger and polarity defines (a09c5ec0) · Commits · 戴 / test

arch/x86/include/asm/mpspec_def.h

+11 −3

Original line number	Diff line number	Diff line
		@@ -128,9 +128,17 @@ enum mp_irq_source_types {
		mp_ExtINT = 3
		};

		#define MP_IRQDIR_DEFAULT 0
		#define MP_IRQDIR_HIGH 1
		#define MP_IRQDIR_LOW 3
		#define MP_IRQPOL_DEFAULT 0x0
		#define MP_IRQPOL_ACTIVE_HIGH 0x1
		#define MP_IRQPOL_RESERVED 0x2
		#define MP_IRQPOL_ACTIVE_LOW 0x3
		#define MP_IRQPOL_MASK 0x3

		#define MP_IRQTRIG_DEFAULT 0x0
		#define MP_IRQTRIG_EDGE 0x4
		#define MP_IRQTRIG_RESERVED 0x8
		#define MP_IRQTRIG_LEVEL 0xc
		#define MP_IRQTRIG_MASK 0xc

		#define MP_APIC_ALL 0xFF

arch/x86/kernel/apic/io_apic.c

+10 −10

Original line number	Diff line number	Diff line
		@@ -800,18 +800,18 @@ static int irq_polarity(int idx)
		/*
		* Determine IRQ line polarity (high active or low active):
		*/
		switch (mp_irqs[idx].irqflag & 0x03) {
		case 0:
		switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
		case MP_IRQPOL_DEFAULT:
		/* conforms to spec, ie. bus-type dependent polarity */
		if (test_bit(bus, mp_bus_not_pci))
		return default_ISA_polarity(idx);
		else
		return default_PCI_polarity(idx);
		case 1:
		case MP_IRQPOL_ACTIVE_HIGH:
		return IOAPIC_POL_HIGH;
		case 2:
		case MP_IRQPOL_RESERVED:
		pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
		case 3:
		case MP_IRQPOL_ACTIVE_LOW:
		default: /* Pointless default required due to do gcc stupidity */
		return IOAPIC_POL_LOW;
		}
		@@ -845,8 +845,8 @@ static int irq_trigger(int idx)
		/*
		* Determine IRQ trigger mode (edge or level sensitive):
		*/
		switch ((mp_irqs[idx].irqflag >> 2) & 0x03) {
		case 0:
		switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
		case MP_IRQTRIG_DEFAULT:
		/* conforms to spec, ie. bus-type dependent trigger mode */
		if (test_bit(bus, mp_bus_not_pci))
		trigger = default_ISA_trigger(idx);
		@@ -854,11 +854,11 @@ static int irq_trigger(int idx)
		trigger = default_PCI_trigger(idx);
		/* Take EISA into account */
		return eisa_irq_trigger(idx, bus, trigger);
		case 1:
		case MP_IRQTRIG_EDGE:
		return IOAPIC_EDGE;
		case 2:
		case MP_IRQTRIG_RESERVED:
		pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
		case 3:
		case MP_IRQTRIG_LEVEL:
		default: /* Pointless default required due to do gcc stupidity */
		return IOAPIC_LEVEL;
		}

arch/x86/kernel/mpparse.c

+14 −9

Original line number	Diff line number	Diff line
		@@ -281,7 +281,7 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
		int ELCR_fallback = 0;

		intsrc.type = MP_INTSRC;
		intsrc.irqflag = 0; /* conforming */
		intsrc.irqflag = MP_IRQTRIG_DEFAULT \| MP_IRQPOL_DEFAULT;
		intsrc.srcbus = 0;
		intsrc.dstapic = mpc_ioapic_id(0);

		@@ -324,10 +324,13 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
		* copy that information over to the MP table in the
		* irqflag field (level sensitive, active high polarity).
		*/
		if (ELCR_trigger(i))
		intsrc.irqflag = 13;
		else
		intsrc.irqflag = 0;
		if (ELCR_trigger(i)) {
		intsrc.irqflag = MP_IRQTRIG_LEVEL \|
		MP_IRQPOL_ACTIVE_HIGH;
		} else {
		intsrc.irqflag = MP_IRQTRIG_DEFAULT \|
		MP_IRQPOL_DEFAULT;
		}
		}

		intsrc.srcbusirq = i;
		@@ -419,7 +422,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
		construct_ioapic_table(mpc_default_type);

		lintsrc.type = MP_LINTSRC;
		lintsrc.irqflag = 0; /* conforming */
		lintsrc.irqflag = MP_IRQTRIG_DEFAULT \| MP_IRQPOL_DEFAULT;
		lintsrc.srcbusid = 0;
		lintsrc.srcbusirq = 0;
		lintsrc.destapic = MP_APIC_ALL;
		@@ -664,7 +667,7 @@ static int __init get_MP_intsrc_index(struct mpc_intsrc *m)
		if (m->irqtype != mp_INT)
		return 0;

		if (m->irqflag != 0x0f)
		if (m->irqflag != (MP_IRQTRIG_LEVEL \| MP_IRQPOL_ACTIVE_LOW))
		return 0;

		/* not legacy */
		@@ -673,7 +676,8 @@ static int __init get_MP_intsrc_index(struct mpc_intsrc *m)
		if (mp_irqs[i].irqtype != mp_INT)
		continue;

		if (mp_irqs[i].irqflag != 0x0f)
		if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL \|
		MP_IRQPOL_ACTIVE_LOW))
		continue;

		if (mp_irqs[i].srcbus != m->srcbus)
		@@ -784,7 +788,8 @@ static int __init replace_intsrc_all(struct mpc_table *mpc,
		if (mp_irqs[i].irqtype != mp_INT)
		continue;

		if (mp_irqs[i].irqflag != 0x0f)
		if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL \|
		MP_IRQPOL_ACTIVE_LOW))
		continue;

		if (nr_m_spare > 0) {

arch/x86/platform/intel-mid/sfi.c

+2 −3

Original line number	Diff line number	Diff line
		@@ -96,8 +96,7 @@ int __init sfi_parse_mtmr(struct sfi_table_header *table)
		pentry->freq_hz, pentry->irq);
		mp_irq.type = MP_INTSRC;
		mp_irq.irqtype = mp_INT;
		/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
		mp_irq.irqflag = 5;
		mp_irq.irqflag = MP_IRQTRIG_EDGE \| MP_IRQPOL_ACTIVE_HIGH;
		mp_irq.srcbus = MP_BUS_ISA;
		mp_irq.srcbusirq = pentry->irq; /* IRQ */
		mp_irq.dstapic = MP_APIC_ALL;
		@@ -168,7 +167,7 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
		totallen, (u32)pentry->phys_addr, pentry->irq);
		mp_irq.type = MP_INTSRC;
		mp_irq.irqtype = mp_INT;
		mp_irq.irqflag = 0xf; /* level trigger and active low */
		mp_irq.irqflag = MP_IRQTRIG_LEVEL \| MP_IRQPOL_ACTIVE_LOW;
		mp_irq.srcbus = MP_BUS_ISA;
		mp_irq.srcbusirq = pentry->irq; /* IRQ */
		mp_irq.dstapic = MP_APIC_ALL;

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