Commit a08c832f authored Dec 09, 2017 by Eugeniy Paltsev Committed by Vineet Gupta Dec 20, 2017

ARC: [plat-hsdk]: Set initial core pll output frequency



Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

parent c18fc907

arch/arc/boot/dts/hsdk.dts

+8 −0

Original line number	Diff line number	Diff line
		@@ -114,6 +114,14 @@
		reg = <0x00 0x10>, <0x14B8 0x4>;
		#clock-cells = <0>;
		clocks = <&input_clk>;

		/*
		* Set initial core pll output frequency to 1GHz.
		* It will be applied at the core pll driver probing
		* on early boot.
		*/
		assigned-clocks = <&core_clk>;
		assigned-clock-rates = <1000000000>;
		};

		serial: serial@5000 {

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