Commit a04ac827 authored Oct 15, 2020 by Chris Wilson

drm/i915/gt: Fixup tgl mocs for PTE tracking



Forcing mocs:1 [used for our winsys follows-pte mode] to be cached
caused display glitches. Though it is documented as deprecated (and so
likely behaves as uncached) use the follow-pte bit and force it out of
L3 cache.

Fixes: 4d8a5cfe ("drm/i915/gt: Initialize reserved and unspecified MOCS indices")
Testcase: igt/kms_frontbuffer_tracking
Testcase: igt/kms_big_fb
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201015122138.30161-4-chris@chris-wilson.co.uk

parent c0888e9e

drivers/gpu/drm/i915/gt/intel_mocs.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -243,8 +243,9 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
		* only, __init_mocs_table() take care to program unused index with
		* this entry.
		*/
		MOCS_ENTRY(1, LE_3_WB \| LE_TC_1_LLC \| LE_LRUM(3),
		L3_3_WB),
		MOCS_ENTRY(I915_MOCS_PTE,
		LE_0_PAGETABLE \| LE_TC_0_PAGETABLE,
		L3_1_UC),
		GEN11_MOCS_ENTRIES,

		/* Implicitly enable L1 - HDC:L1 + L3 + LLC */

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