drm/i915: Mark up debugfs with rpm wakeref tracking

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	intel_wakeref_t wakeref;

	int i, pipe;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	if (IS_CHERRYVIEW(dev_priv)) {

		seq_printf(m, "Master Interrupt Control:\t%08x\n",

		}

	}

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

{

	struct drm_i915_private *i915 = inode->i_private;

	struct i915_gpu_state *gpu;

	intel_wakeref_t wakeref;

	intel_runtime_pm_get(i915);

	wakeref = intel_runtime_pm_get(i915);

	gpu = i915_capture_gpu_state(i915);

	intel_runtime_pm_put_unchecked(i915);

	intel_runtime_pm_put(i915, wakeref);

	if (IS_ERR(gpu))

		return PTR_ERR(gpu);

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_rps *rps = &dev_priv->gt_pm.rps;

	intel_wakeref_t wakeref;

	int ret = 0;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	if (IS_GEN(dev_priv, 5)) {

		u16 rgvswctl = I915_READ16(MEMSWCTL);

	seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);

	seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return ret;

}

	u64 acthd[I915_NUM_ENGINES];

	u32 seqno[I915_NUM_ENGINES];

	struct intel_instdone instdone;

	intel_wakeref_t wakeref;

	enum intel_engine_id id;

	if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))

		return 0;

	}

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	for_each_engine(engine, dev_priv, id) {

		acthd[id] = intel_engine_get_active_head(engine);

	intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))

		seq_printf(m, "Hangcheck active, timer fires in %dms\n",

static int i915_drpc_info(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	int err;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		err = vlv_drpc_info(m);

	else

		err = ironlake_drpc_info(m);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return err;

}

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_fbc *fbc = &dev_priv->fbc;

	intel_wakeref_t wakeref;

	if (!HAS_FBC(dev_priv))

		return -ENODEV;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	mutex_lock(&fbc->lock);

	if (intel_fbc_is_active(dev_priv))

	}

	mutex_unlock(&fbc->lock);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

static int i915_ips_status(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	if (!HAS_IPS(dev_priv))

		return -ENODEV;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	seq_printf(m, "Enabled by kernel parameter: %s\n",

		   yesno(i915_modparams.enable_ips));

			seq_puts(m, "Currently: disabled\n");

	}

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

static int i915_sr_status(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	bool sr_enabled = false;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

	if (INTEL_GEN(dev_priv) >= 9)

		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct drm_device *dev = &dev_priv->drm;

	unsigned long temp, chipset, gfx;

	intel_wakeref_t wakeref;

	int ret;

	if (!IS_GEN(dev_priv, 5))

		return -ENODEV;

	intel_runtime_pm_get(dev_priv);

	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	wakeref = intel_runtime_pm_get(dev_priv);

	temp = i915_mch_val(dev_priv);

	chipset = i915_chipset_val(dev_priv);

	gfx = i915_gfx_val(dev_priv);

	mutex_unlock(&dev->struct_mutex);

	intel_runtime_pm_put(dev_priv, wakeref);

	seq_printf(m, "GMCH temp: %ld\n", temp);

	seq_printf(m, "Chipset power: %ld\n", chipset);

	seq_printf(m, "GFX power: %ld\n", gfx);

	seq_printf(m, "Total power: %ld\n", chipset + gfx);

	intel_runtime_pm_put_unchecked(dev_priv);

	return 0;

}

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_rps *rps = &dev_priv->gt_pm.rps;

	unsigned int max_gpu_freq, min_gpu_freq;

	intel_wakeref_t wakeref;

	int gpu_freq, ia_freq;

	int ret;

	if (!HAS_LLC(dev_priv))

		return -ENODEV;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	ret = mutex_lock_interruptible(&dev_priv->pcu_lock);

	if (ret)

	mutex_unlock(&dev_priv->pcu_lock);

out:

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return ret;

}

static int i915_swizzle_info(struct seq_file *m, void *data)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",

		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));

	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)

		seq_puts(m, "L-shaped memory detected\n");

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

	struct drm_device *dev = &dev_priv->drm;

	struct intel_rps *rps = &dev_priv->gt_pm.rps;

	u32 act_freq = rps->cur_freq;

	intel_wakeref_t wakeref;

	struct drm_file *file;

	if (intel_runtime_pm_get_if_in_use(dev_priv)) {

	wakeref = intel_runtime_pm_get_if_in_use(dev_priv);

	if (wakeref) {

		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

			mutex_lock(&dev_priv->pcu_lock);

			act_freq = vlv_punit_read(dev_priv,

			act_freq = intel_get_cagf(dev_priv,

						  I915_READ(GEN6_RPSTAT1));

		}

		intel_runtime_pm_put_unchecked(dev_priv);

		intel_runtime_pm_put(dev_priv, wakeref);

	}

	seq_printf(m, "RPS enabled? %d\n", rps->enabled);

static int i915_huc_load_status_info(struct seq_file *m, void *data)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	struct drm_printer p;

	if (!HAS_HUC(dev_priv))

	p = drm_seq_file_printer(m);

	intel_uc_fw_dump(&dev_priv->huc.fw, &p);

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

static int i915_guc_load_status_info(struct seq_file *m, void *data)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	struct drm_printer p;

	u32 tmp, i;

	p = drm_seq_file_printer(m);

	intel_uc_fw_dump(&dev_priv->guc.fw, &p);

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	tmp = I915_READ(GUC_STATUS);

	for (i = 0; i < 16; i++)

		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

static int i915_edp_psr_status(struct seq_file *m, void *data)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	u32 psrperf = 0;

	bool enabled = false;

	bool sink_support;

	if (!sink_support)

		return 0;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	mutex_lock(&dev_priv->psr.lock);

	seq_printf(m, "PSR mode: %s\n",

			   dev_priv->psr.last_exit);

	}

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

{

	struct drm_i915_private *dev_priv = data;

	struct drm_modeset_acquire_ctx ctx;

	intel_wakeref_t wakeref;

	int ret;

	if (!CAN_PSR(dev_priv))

	DRM_DEBUG_KMS("Setting PSR debug to %llx\n", val);

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);

	drm_modeset_drop_locks(&ctx);

	drm_modeset_acquire_fini(&ctx);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return ret;

}

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	unsigned long long power;

	intel_wakeref_t wakeref;

	u32 units;

	if (INTEL_GEN(dev_priv) < 6)

		return -ENODEV;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {

		intel_runtime_pm_put_unchecked(dev_priv);

		intel_runtime_pm_put(dev_priv, wakeref);

		return -ENODEV;

	}

	power = I915_READ(MCH_SECP_NRG_STTS);

	power = (1000000 * power) >> units; /* convert to uJ */

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	seq_printf(m, "%llu", power);

static int i915_dmc_info(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	struct intel_csr *csr;

	if (!HAS_CSR(dev_priv))

	csr = &dev_priv->csr;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));

	seq_printf(m, "path: %s\n", csr->fw_path);

	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));

	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

	struct intel_crtc *crtc;

	struct drm_connector *connector;

	struct drm_connector_list_iter conn_iter;

	intel_wakeref_t wakeref;

	wakeref = intel_runtime_pm_get(dev_priv);

	intel_runtime_pm_get(dev_priv);

	seq_printf(m, "CRTC info\n");

	seq_printf(m, "---------\n");

	for_each_intel_crtc(dev, crtc) {

	drm_connector_list_iter_end(&conn_iter);

	mutex_unlock(&dev->mode_config.mutex);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_engine_cs *engine;

	intel_wakeref_t wakeref;

	enum intel_engine_id id;

	struct drm_printer p;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	seq_printf(m, "GT awake? %s (epoch %u)\n",

		   yesno(dev_priv->gt.awake), dev_priv->gt.epoch);

	for_each_engine(engine, dev_priv, id)

		intel_engine_dump(engine, &p, "%s\n", engine->name);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

{

	struct seq_file *m = file->private_data;

	struct drm_i915_private *dev_priv = m->private;

	intel_wakeref_t wakeref;

	int ret;

	bool enable;

	if (ret < 0)

		return ret;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	if (!dev_priv->ipc_enabled && enable)

		DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");

	dev_priv->wm.distrust_bios_wm = true;

	dev_priv->ipc_enabled = enable;

	intel_enable_ipc(dev_priv);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return len;

}

i915_drop_caches_set(void *data, u64 val)

{

	struct drm_i915_private *i915 = data;

	intel_wakeref_t wakeref;

	int ret = 0;

	DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",

		  val, val & DROP_ALL);

	intel_runtime_pm_get(i915);

	wakeref = intel_runtime_pm_get(i915);

	if (val & DROP_RESET_ACTIVE && !intel_engines_are_idle(i915))

		i915_gem_set_wedged(i915);

		i915_gem_drain_freed_objects(i915);

out:

	intel_runtime_pm_put_unchecked(i915);

	intel_runtime_pm_put(i915, wakeref);

	return ret;

}

i915_cache_sharing_get(void *data, u64 *val)

{

	struct drm_i915_private *dev_priv = data;

	intel_wakeref_t wakeref;

	u32 snpcr;

	if (!(IS_GEN_RANGE(dev_priv, 6, 7)))

		return -ENODEV;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;

i915_cache_sharing_set(void *data, u64 val)

{

	struct drm_i915_private *dev_priv = data;

	intel_wakeref_t wakeref;

	u32 snpcr;

	if (!(IS_GEN_RANGE(dev_priv, 6, 7)))

	if (val > 3)

		return -EINVAL;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);

	/* Update the cache sharing policy here as well */

	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);

	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct sseu_dev_info sseu;

	intel_wakeref_t wakeref;

	if (INTEL_GEN(dev_priv) < 8)

		return -ENODEV;

	sseu.max_eus_per_subslice =

		RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;

	intel_runtime_pm_get(dev_priv);

	wakeref = intel_runtime_pm_get(dev_priv);

	if (IS_CHERRYVIEW(dev_priv)) {

		cherryview_sseu_device_status(dev_priv, &sseu);

		gen10_sseu_device_status(dev_priv, &sseu);

	}

	intel_runtime_pm_put_unchecked(dev_priv);

	intel_runtime_pm_put(dev_priv, wakeref);

	i915_print_sseu_info(m, false, &sseu);