Commit a028c4b0 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Add FIXME for bdw semaphore detection in hancheck 



Currently not an issue since we don't emit sempahores, but better
not forget about those.

As a little prep work extract the ipehr decoding for cleaner control
flow. And apply a bit of polish.

Cc: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent aa83e30d

drivers/gpu/drm/i915/i915_irq.c

+18 −2
Original line number Diff line number Diff line
@@ -2501,6 +2501,23 @@ ring_idle(struct intel_ring_buffer *ring, u32 seqno) 
		i915_seqno_passed(seqno, ring_last_seqno(ring)));

}



static bool

ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)

{

	if (INTEL_INFO(dev)->gen >= 8) {

		/*

		 * FIXME: gen8 semaphore support - currently we don't emit

		 * semaphores on bdw anyway, but this needs to be addressed when

		 * we merge that code.

		 */

		return false;

	} else {

		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;

		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |

				 MI_SEMAPHORE_REGISTER);

	}

}



static struct intel_ring_buffer *

semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)

{
@@ -2509,8 +2526,7 @@ semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) 
	int i;



	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));

	if ((ipehr & ~(0x3 << 16)) !=

	    (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))

	if (!ipehr_is_semaphore_wait(ring->dev, ipehr))

		return NULL;



	/*

drivers/gpu/drm/i915/i915_reg.h

+2 −1
Original line number Diff line number Diff line
@@ -245,6 +245,7 @@ 
#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define   MI_SEMAPHORE_SYNC_INVALID (3<<16)

#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)

#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)

#define   MI_MM_SPACE_GTT		(1<<8)

#define   MI_MM_SPACE_PHYSICAL		(0<<8)

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