spi: tegra114: dump SPI registers during timeout (a0253c8f) · Commits · 戴 / test

drivers/spi/spi-tegra114.c

+18 −0

Original line number	Diff line number	Diff line
		@@ -874,6 +874,20 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
		tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
		}

		static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
		{
		dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
		dev_dbg(tspi->dev, "Command1: 0x%08x \| Command2: 0x%08x\n",
		tegra_spi_readl(tspi, SPI_COMMAND1),
		tegra_spi_readl(tspi, SPI_COMMAND2));
		dev_dbg(tspi->dev, "DMA_CTL: 0x%08x \| DMA_BLK: 0x%08x\n",
		tegra_spi_readl(tspi, SPI_DMA_CTL),
		tegra_spi_readl(tspi, SPI_DMA_BLK));
		dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x \| FIFO_STATUS: 0x%08x\n",
		tegra_spi_readl(tspi, SPI_TRANS_STATUS),
		tegra_spi_readl(tspi, SPI_FIFO_STATUS));
		}

		static int tegra_spi_transfer_one_message(struct spi_master *master,
		struct spi_message *msg)
		{
		@@ -920,6 +934,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
		(tspi->cur_direction & DATA_DIR_RX))
		dmaengine_terminate_all(tspi->rx_dma_chan);
		ret = -EIO;
		tegra_spi_dump_regs(tspi);
		tegra_spi_flush_fifos(tspi);
		reset_control_assert(tspi->rst);
		udelay(2);
		@@ -930,6 +945,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
		if (tspi->tx_status \|\| tspi->rx_status) {
		dev_err(tspi->dev, "Error in Transfer\n");
		ret = -EIO;
		tegra_spi_dump_regs(tspi);
		goto complete_xfer;
		}
		msg->actual_length += xfer->len;
		@@ -971,6 +987,7 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
		tspi->status_reg);
		dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
		tspi->command1_reg, tspi->dma_control_reg);
		tegra_spi_dump_regs(tspi);
		tegra_spi_flush_fifos(tspi);
		complete(&tspi->xfer_completion);
		spin_unlock_irqrestore(&tspi->lock, flags);
		@@ -1045,6 +1062,7 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
		tspi->status_reg);
		dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
		tspi->command1_reg, tspi->dma_control_reg);
		tegra_spi_dump_regs(tspi);
		tegra_spi_flush_fifos(tspi);
		complete(&tspi->xfer_completion);
		spin_unlock_irqrestore(&tspi->lock, flags);

Admin message