Commit a0227083 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sti-dt-for-v4.3-1' of... 

Merge tag 'sti-dt-for-v4.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/dt

STi DT update for v4.3, round 1.

Highlights:
-----------
 - Add pinctrl configurations for transport stream channels
 - Add cpu-release-addr properties to STiH407 and STiH418
 - Add PWM regulator support so STIH407 family
 - Add BDISP node to STiH407

* tag 'sti-dt-for-v4.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti

:
  ARM: DT: STiH410: Add bdisp dt nodes
  ARM: STi: STiH407: Add PWM Regulator node
  ARM: STi: STiH407: Move PWM nodes STiH407 => STiH407-family
  ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
  ARM: STi: DT: STiH418: Add cpu-release-addr dt property.
  ARM: STi: DT: STiH407: Add cpu-release-addr dt property.
  ARM: STi: DT: Add STiH407 family mtsin0 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsout1 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsout0 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsin5 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsin4 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsin3 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsin2 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsin1 pinctrl configuration
  ARM: STi: DT: Add STiH407 family tsin0 pinctrl configuration

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 9e3cffd8 79444509

Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

+2 −2
Original line number Diff line number Diff line
@@ -21,8 +21,8 @@ Required properties: 
	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-c0_0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-c0_1",	"st,clkgen-plls-c32"

	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"

	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"



	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"

	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"

arch/arm/boot/dts/stih407-clock.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ 


			clk_s_c0_pll0: clk-s-c0-pll0 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;
@@ -143,7 +143,7 @@ 


			clk_s_c0_pll1: clk-s-c0-pll1 {

				#clock-cells = <1>;

				compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";

				compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;

arch/arm/boot/dts/stih407-family.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -22,11 +22,15 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			/* u-boot puts hpen in SBC dmem at 0xa4 offset */

			cpu-release-addr = <0x94100A4>;

		};

		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			/* u-boot puts hpen in SBC dmem at 0xa4 offset */

			cpu-release-addr = <0x94100A4>;

		};

	};
@@ -65,6 +69,17 @@ 
		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;

	};



	pwm_regulator: pwm-regulator {

		compatible = "pwm-regulator";

		pwms = <&pwm1 3 8448>;

		regulator-name = "CPU_1V0_AVS";

		regulator-min-microvolt = <784000>;

		regulator-max-microvolt = <1299000>;

		regulator-always-on;

		max-duty-cycle = <255>;

		status = "okay";

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;
@@ -539,6 +554,7 @@ 
			status = "disabled";

		};





		st_dwc3: dwc3@8f94000 {

			compatible	= "st,stih407-dwc3";

			reg		= <0x08f94000 0x1000>, <0x110 0x4>;
@@ -565,5 +581,34 @@ 
						  <&phy_port2 PHY_TYPE_USB3>;

			};

		};



		/* COMMS PWM Module */

		pwm0: pwm@9810000 {

			compatible	= "st,sti-pwm";

			status		= "okay";

			#pwm-cells	= <2>;

			reg		= <0x9810000 0x68>;

			pinctrl-names	= "default";

			pinctrl-0	= <&pinctrl_pwm0_chan0_default>;

			clock-names	= "pwm";

			clocks		= <&clk_sysin>;

			st,pwm-num-chan = <1>;

		};



		/* SBC PWM Module */

		pwm1: pwm@9510000 {

			compatible	= "st,sti-pwm";

			status		= "okay";

			#pwm-cells	= <2>;

			reg		= <0x9510000 0x68>;

			pinctrl-names	= "default";

			pinctrl-0	= <&pinctrl_pwm1_chan0_default

					&pinctrl_pwm1_chan1_default

					&pinctrl_pwm1_chan2_default

					&pinctrl_pwm1_chan3_default>;

			clock-names	= "pwm";

			clocks		= <&clk_sysin>;

			st,pwm-num-chan = <4>;

		};

	};

};

arch/arm/boot/dts/stih407-pinctrl.dtsi

+200 −0
Original line number Diff line number Diff line
@@ -439,6 +439,194 @@ 
					};

				};

			};



			tsin0 {

				pinctrl_tsin0_parallel: tsin0_parallel {

					st,pins {

						DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

				pinctrl_tsin0_serial: tsin0_serial {

					st,pins {

						DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			tsin1 {

				pinctrl_tsin1_parallel: tsin1_parallel {

					st,pins {

						DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

				pinctrl_tsin1_serial: tsin1_serial {

					st,pins {

						DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			tsin2 {

				pinctrl_tsin2_parallel: tsin2_parallel {

					st,pins {

						DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;

						DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;

						DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;

						DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;

						DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;

						DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;

						DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

				pinctrl_tsin2_serial: tsin2_serial {

					st,pins {

						DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			tsin3 {

				pinctrl_tsin3_serial: tsin3_serial {

					st,pins {

						DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			tsin4 {

				pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {

					st,pins {

						DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;

						ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;

						PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			tsin5 {

				pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {

					st,pins {

						DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

				pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {

					st,pins {

						DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			tsout0 {

				pinctrl_tsout0_parallel: tsout0_parallel {

					st,pins {

						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;

						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

					};

				};

				pinctrl_tsout0_serial: tsout0_serial {

					st,pins {

						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;

						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			tsout1 {

				pinctrl_tsout1_serial: tsout1_serial {

					st,pins {

						DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;

						VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			mtsin0 {

				pinctrl_mtsin0_parallel: mtsin0_parallel {

					st,pins {

						DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};

		};



		pin-controller-front1 {
@@ -452,6 +640,18 @@ 
			interrupts-names = "irqmux";

			ranges = <0 0x09210000 0x10000>;



			tsin4 {

				pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {

					st,pins {

						DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;

						VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;

					};

				};

			};



			pio20: pio@09210000 {

				gpio-controller;

				#gpio-cells = <1>;

arch/arm/boot/dts/stih407.dtsi

+0 −28
Original line number Diff line number Diff line
@@ -147,33 +147,5 @@ 
				};

			};

		};



		/* COMMS PWM Module */

		pwm0: pwm@9810000 {

			compatible	= "st,sti-pwm";

			status		= "disabled";

			#pwm-cells	= <2>;

			reg		= <0x9810000 0x68>;

			pinctrl-names	= "default";

			pinctrl-0	= <&pinctrl_pwm0_chan0_default>;

			clock-names	= "pwm";

			clocks		= <&clk_sysin>;

		};



		/* SBC PWM Module */

		pwm1: pwm@9510000 {

			compatible	= "st,sti-pwm";

			status		= "disabled";

			#pwm-cells	= <2>;

			reg		= <0x9510000 0x68>;

			pinctrl-names	= "default";

			pinctrl-0	= <&pinctrl_pwm1_chan0_default

					&pinctrl_pwm1_chan1_default

					&pinctrl_pwm1_chan2_default

					&pinctrl_pwm1_chan3_default>;

			clock-names	= "pwm";

			clocks		= <&clk_sysin>;

			st,pwm-num-chan = <4>;

		};

	};

};

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