Commit a0204f25 authored by Dong Aisheng's avatar Dong Aisheng Committed by Greg Kroah-Hartman
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tty: serial: lpuart: refactor lpuart32_{read|write} prototype 



Due to the original lpuart32_read/write takes no port specific
information arguments, it's hard to distinguish port difference
within the API. Although it works before, but not suitable anymore
when adding more new chips support.

So let's convert it to accept a new struct uart_port argument
to make it be able to retrieve more port specific information.
This is a preparation for the later adding new chips support
more easily. No functions changes.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Cc: Fugang Duan <fugang.duan@nxp.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0d6fce90

drivers/tty/serial/fsl_lpuart.c

+62 −61
Original line number Diff line number Diff line
@@ -279,14 +279,15 @@ MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 
/* Forward declare this for the dma callbacks*/

static void lpuart_dma_tx_complete(void *arg);



static u32 lpuart32_read(void __iomem *addr)

static inline u32 lpuart32_read(struct uart_port *port, u32 reg_off)

{

	return ioread32be(addr);

	return ioread32be(port->membase + reg_off);

}



static void lpuart32_write(u32 val, void __iomem *addr)

static inline void lpuart32_write(struct uart_port *port, u32 val,

				  u32 reg_off)

{

	iowrite32be(val, addr);

	iowrite32be(val, port->membase + reg_off);

}



static void lpuart_stop_tx(struct uart_port *port)
@@ -302,9 +303,9 @@ static void lpuart32_stop_tx(struct uart_port *port) 
{

	unsigned long temp;



	temp = lpuart32_read(port->membase + UARTCTRL);

	temp = lpuart32_read(port, UARTCTRL);

	temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);

	lpuart32_write(temp, port->membase + UARTCTRL);

	lpuart32_write(port, temp, UARTCTRL);

}



static void lpuart_stop_rx(struct uart_port *port)
@@ -319,8 +320,8 @@ static void lpuart32_stop_rx(struct uart_port *port) 
{

	unsigned long temp;



	temp = lpuart32_read(port->membase + UARTCTRL);

	lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);

	temp = lpuart32_read(port, UARTCTRL);

	lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);

}



static void lpuart_dma_tx(struct lpuart_port *sport)
@@ -519,14 +520,14 @@ static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 
	struct circ_buf *xmit = &sport->port.state->xmit;

	unsigned long txcnt;



	txcnt = lpuart32_read(sport->port.membase + UARTWATER);

	txcnt = lpuart32_read(&sport->port, UARTWATER);

	txcnt = txcnt >> UARTWATER_TXCNT_OFF;

	txcnt &= UARTWATER_COUNT_MASK;

	while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {

		lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);

		lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);

		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);

		sport->port.icount.tx++;

		txcnt = lpuart32_read(sport->port.membase + UARTWATER);

		txcnt = lpuart32_read(&sport->port, UARTWATER);

		txcnt = txcnt >> UARTWATER_TXCNT_OFF;

		txcnt &= UARTWATER_COUNT_MASK;

	}
@@ -562,10 +563,10 @@ static void lpuart32_start_tx(struct uart_port *port) 
	struct lpuart_port *sport = container_of(port, struct lpuart_port, port);

	unsigned long temp;



	temp = lpuart32_read(port->membase + UARTCTRL);

	lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);

	temp = lpuart32_read(port, UARTCTRL);

	lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);



	if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)

	if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)

		lpuart32_transmit_buffer(sport);

}
@@ -588,7 +589,7 @@ static unsigned int lpuart_tx_empty(struct uart_port *port) 


static unsigned int lpuart32_tx_empty(struct uart_port *port)

{

	return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?

	return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?

		TIOCSER_TEMT : 0;

}
@@ -601,7 +602,7 @@ static irqreturn_t lpuart_txint(int irq, void *dev_id) 
	spin_lock_irqsave(&sport->port.lock, flags);

	if (sport->port.x_char) {

		if (sport->port.iotype & UPIO_MEM32BE)

			lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);

			lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);

		else

			writeb(sport->port.x_char, sport->port.membase + UARTDR);

		goto out;
@@ -701,15 +702,15 @@ static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 


	spin_lock_irqsave(&sport->port.lock, flags);



	while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {

	while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {

		flg = TTY_NORMAL;

		sport->port.icount.rx++;

		/*

		 * to clear the FE, OR, NF, FE, PE flags,

		 * read STAT then read DATA reg

		 */

		sr = lpuart32_read(sport->port.membase + UARTSTAT);

		rx = lpuart32_read(sport->port.membase + UARTDATA);

		sr = lpuart32_read(&sport->port, UARTSTAT);

		rx = lpuart32_read(&sport->port, UARTDATA);

		rx &= 0x3ff;



		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
@@ -776,18 +777,18 @@ static irqreturn_t lpuart32_int(int irq, void *dev_id) 
	struct lpuart_port *sport = dev_id;

	unsigned long sts, rxcount;



	sts = lpuart32_read(sport->port.membase + UARTSTAT);

	rxcount = lpuart32_read(sport->port.membase + UARTWATER);

	sts = lpuart32_read(&sport->port, UARTSTAT);

	rxcount = lpuart32_read(&sport->port, UARTWATER);

	rxcount = rxcount >> UARTWATER_RXCNT_OFF;



	if (sts & UARTSTAT_RDRF || rxcount > 0)

		lpuart32_rxint(irq, dev_id);



	if ((sts & UARTSTAT_TDRE) &&

		!(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))

		!(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))

		lpuart_txint(irq, dev_id);



	lpuart32_write(sts, sport->port.membase + UARTSTAT);

	lpuart32_write(&sport->port, sts, UARTSTAT);

	return IRQ_HANDLED;

}
@@ -1048,7 +1049,7 @@ static unsigned int lpuart32_get_mctrl(struct uart_port *port) 
	unsigned int temp = 0;

	unsigned long reg;



	reg = lpuart32_read(port->membase + UARTMODIR);

	reg = lpuart32_read(port, UARTMODIR);

	if (reg & UARTMODIR_TXCTSE)

		temp |= TIOCM_CTS;
@@ -1083,7 +1084,7 @@ static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 
{

	unsigned long temp;



	temp = lpuart32_read(port->membase + UARTMODIR) &

	temp = lpuart32_read(port, UARTMODIR) &

			~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);



	if (mctrl & TIOCM_RTS)
@@ -1092,7 +1093,7 @@ static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 
	if (mctrl & TIOCM_CTS)

		temp |= UARTMODIR_TXCTSE;



	lpuart32_write(temp, port->membase + UARTMODIR);

	lpuart32_write(port, temp, UARTMODIR);

}



static void lpuart_break_ctl(struct uart_port *port, int break_state)
@@ -1111,12 +1112,12 @@ static void lpuart32_break_ctl(struct uart_port *port, int break_state) 
{

	unsigned long temp;



	temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;

	temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;



	if (break_state != 0)

		temp |= UARTCTRL_SBK;



	lpuart32_write(temp, port->membase + UARTCTRL);

	lpuart32_write(port, temp, UARTCTRL);

}



static void lpuart_setup_watermark(struct lpuart_port *sport)
@@ -1156,24 +1157,24 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport) 
	unsigned long val, ctrl;

	unsigned long ctrl_saved;



	ctrl = lpuart32_read(sport->port.membase + UARTCTRL);

	ctrl = lpuart32_read(&sport->port, UARTCTRL);

	ctrl_saved = ctrl;

	ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |

			UARTCTRL_RIE | UARTCTRL_RE);

	lpuart32_write(ctrl, sport->port.membase + UARTCTRL);

	lpuart32_write(&sport->port, ctrl, UARTCTRL);



	/* enable FIFO mode */

	val = lpuart32_read(sport->port.membase + UARTFIFO);

	val = lpuart32_read(&sport->port, UARTFIFO);

	val |= UARTFIFO_TXFE | UARTFIFO_RXFE;

	val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;

	lpuart32_write(val, sport->port.membase + UARTFIFO);

	lpuart32_write(&sport->port, val, UARTFIFO);



	/* set the watermark */

	val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);

	lpuart32_write(val, sport->port.membase + UARTWATER);

	lpuart32_write(&sport->port, val, UARTWATER);



	/* Restore cr2 */

	lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);

	lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);

}



static void rx_dma_timer_init(struct lpuart_port *sport)
@@ -1249,7 +1250,7 @@ static int lpuart32_startup(struct uart_port *port) 
	unsigned long temp;



	/* determine FIFO size */

	temp = lpuart32_read(sport->port.membase + UARTFIFO);

	temp = lpuart32_read(&sport->port, UARTFIFO);



	sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &

		UARTFIFO_FIFOSIZE_MASK) - 1);
@@ -1266,10 +1267,10 @@ static int lpuart32_startup(struct uart_port *port) 


	lpuart32_setup_watermark(sport);



	temp = lpuart32_read(sport->port.membase + UARTCTRL);

	temp = lpuart32_read(&sport->port, UARTCTRL);

	temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);

	temp |= UARTCTRL_ILIE;

	lpuart32_write(temp, sport->port.membase + UARTCTRL);

	lpuart32_write(&sport->port, temp, UARTCTRL);



	spin_unlock_irqrestore(&sport->port.lock, flags);

	return 0;
@@ -1318,10 +1319,10 @@ static void lpuart32_shutdown(struct uart_port *port) 
	spin_lock_irqsave(&port->lock, flags);



	/* disable Rx/Tx and interrupts */

	temp = lpuart32_read(port->membase + UARTCTRL);

	temp = lpuart32_read(port, UARTCTRL);

	temp &= ~(UARTCTRL_TE | UARTCTRL_RE |

			UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);

	lpuart32_write(temp, port->membase + UARTCTRL);

	lpuart32_write(port, temp, UARTCTRL);



	spin_unlock_irqrestore(&port->lock, flags);
@@ -1496,9 +1497,9 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 
	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;

	unsigned int sbr;



	ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);

	bd = lpuart32_read(sport->port.membase + UARTBAUD);

	modem = lpuart32_read(sport->port.membase + UARTMODIR);

	ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);

	bd = lpuart32_read(&sport->port, UARTBAUD);

	modem = lpuart32_read(&sport->port, UARTMODIR);

	/*

	 * only support CS8 and CS7, and for CS7 must enable PE.

	 * supported mode:
@@ -1584,21 +1585,21 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 
	uart_update_timeout(port, termios->c_cflag, baud);



	/* wait transmit engin complete */

	while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))

	while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))

		barrier();



	/* disable transmit and receive */

	lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),

			sport->port.membase + UARTCTRL);

	lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),

		       UARTCTRL);



	sbr = sport->port.uartclk / (16 * baud);

	bd &= ~UARTBAUD_SBR_MASK;

	bd |= sbr & UARTBAUD_SBR_MASK;

	bd |= UARTBAUD_BOTHEDGE;

	bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);

	lpuart32_write(bd, sport->port.membase + UARTBAUD);

	lpuart32_write(modem, sport->port.membase + UARTMODIR);

	lpuart32_write(ctrl, sport->port.membase + UARTCTRL);

	lpuart32_write(&sport->port, bd, UARTBAUD);

	lpuart32_write(&sport->port, modem, UARTMODIR);

	lpuart32_write(&sport->port, ctrl, UARTCTRL);

	/* restore control register */



	spin_unlock_irqrestore(&sport->port.lock, flags);
@@ -1701,10 +1702,10 @@ static void lpuart_console_putchar(struct uart_port *port, int ch) 


static void lpuart32_console_putchar(struct uart_port *port, int ch)

{

	while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))

	while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))

		barrier();



	lpuart32_write(ch, port->membase + UARTDATA);

	lpuart32_write(port, ch, UARTDATA);

}



static void
@@ -1752,18 +1753,18 @@ lpuart32_console_write(struct console *co, const char *s, unsigned int count) 
		spin_lock_irqsave(&sport->port.lock, flags);



	/* first save CR2 and then disable interrupts */

	cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);

	cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);

	cr |= (UARTCTRL_TE |  UARTCTRL_RE);

	cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);

	lpuart32_write(cr, sport->port.membase + UARTCTRL);

	lpuart32_write(&sport->port, cr, UARTCTRL);



	uart_console_write(&sport->port, s, count, lpuart32_console_putchar);



	/* wait for transmitter finish complete and restore CR2 */

	while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))

	while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))

		barrier();



	lpuart32_write(old_cr, sport->port.membase + UARTCTRL);

	lpuart32_write(&sport->port, old_cr, UARTCTRL);



	if (locked)

		spin_unlock_irqrestore(&sport->port.lock, flags);
@@ -1829,14 +1830,14 @@ lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 
	unsigned long cr, bd;

	unsigned int sbr, uartclk, baud_raw;



	cr = lpuart32_read(sport->port.membase + UARTCTRL);

	cr = lpuart32_read(&sport->port, UARTCTRL);

	cr &= UARTCTRL_TE | UARTCTRL_RE;

	if (!cr)

		return;



	/* ok, the port was enabled */



	cr = lpuart32_read(sport->port.membase + UARTCTRL);

	cr = lpuart32_read(&sport->port, UARTCTRL);



	*parity = 'n';

	if (cr & UARTCTRL_PE) {
@@ -1851,7 +1852,7 @@ lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 
	else

		*bits = 8;



	bd = lpuart32_read(sport->port.membase + UARTBAUD);

	bd = lpuart32_read(&sport->port, UARTBAUD);

	bd &= UARTBAUD_SBR_MASK;

	sbr = bd;

	uartclk = clk_get_rate(sport->clk);
@@ -2095,9 +2096,9 @@ static int lpuart_suspend(struct device *dev) 


	if (sport->port.iotype & UPIO_MEM32BE) {

		/* disable Rx/Tx and interrupts */

		temp = lpuart32_read(sport->port.membase + UARTCTRL);

		temp = lpuart32_read(&sport->port, UARTCTRL);

		temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);

		lpuart32_write(temp, sport->port.membase + UARTCTRL);

		lpuart32_write(&sport->port, temp, UARTCTRL);

	} else {

		/* disable Rx/Tx and interrupts */

		temp = readb(sport->port.membase + UARTCR2);
@@ -2146,10 +2147,10 @@ static int lpuart_resume(struct device *dev) 


	if (sport->port.iotype & UPIO_MEM32BE) {

		lpuart32_setup_watermark(sport);

		temp = lpuart32_read(sport->port.membase + UARTCTRL);

		temp = lpuart32_read(&sport->port, UARTCTRL);

		temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |

			 UARTCTRL_TE | UARTCTRL_ILIE);

		lpuart32_write(temp, sport->port.membase + UARTCTRL);

		lpuart32_write(&sport->port, temp, UARTCTRL);

	} else {

		lpuart_setup_watermark(sport);

		temp = readb(sport->port.membase + UARTCR2);

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