parisc: Change L1_CACHE_BYTES to 16 (a01fece2) · Commits · 戴 / test

Change L1_CACHE_BYTES to 16 bytes. Tested for 16 days on rp3440. Additional remarks from Helge Deller: Saves ~17 kb of kernel code/data and gives a slight performance improvement in various test cases. Signed-off-by:

John David Anglin <dave.anglin@bell.net> Signed-off-by:

Helge Deller <deller@gmx.de>

arch/parisc/include/asm/cache.h

+5 −13

Original line number	Diff line number	Diff line
		@@ -7,20 +7,12 @@


		/*
		* PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
		* 32-byte cachelines. The default configuration is not for SMP anyway,
		* so if you're building for SMP, you should select the appropriate
		* processor type. There is a potential livelock danger when running
		* a machine with this value set too small, but it's more probable you'll
		* just ruin performance.
		* PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
		* have 32-byte cachelines. The L1 length appears to be 16 bytes but this
		* is not clearly documented.
		*/
		#ifdef CONFIG_PA20
		#define L1_CACHE_BYTES 64
		#define L1_CACHE_SHIFT 6
		#else
		#define L1_CACHE_BYTES 32
		#define L1_CACHE_SHIFT 5
		#endif
		#define L1_CACHE_BYTES 16
		#define L1_CACHE_SHIFT 4

		#ifndef __ASSEMBLY__

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