mxc: TrustZone interrupt controller (TZIC) for Freescale i.MX5 family (a003708a) · Commits · 戴 / test

arch/arm/plat-mxc/Kconfig

+8 −0

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		@@ -62,6 +62,14 @@ config MXC_IRQ_PRIOR
		requirements for timing.
		Say N here, unless you have a specialized requirement.

		config MXC_TZIC
		bool "Enable TrustZone Interrupt Controller"
		depends on ARCH_MX51
		help
		This will be automatically selected for all processors
		containing this interrupt controller.
		Say N here only if you are really sure.

		config MXC_PWM
		tristate "Enable PWM driver"
		depends on ARCH_MXC

+3 −0

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		@@ -5,6 +5,9 @@
		# Common support
		obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o

		# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
		obj-$(CONFIG_MXC_TZIC) += tzic.o

		obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
		obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
		CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS

+1 −0

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		@@ -22,6 +22,7 @@ extern void mx31_map_io(void);
		extern void mx35_map_io(void);
		extern void mxc91231_map_io(void);
		extern void mxc_init_irq(void __iomem *);
		extern void tzic_init_irq(void __iomem *);
		extern void mx1_init_irq(void);
		extern void mx21_init_irq(void);
		extern void mx25_init_irq(void);

+33 −1

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		/*
		* Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
		* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
		* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
		*/

		/*
		@@ -18,11 +18,16 @@
		.endm

		.macro get_irqnr_preamble, base, tmp
		#ifndef CONFIG_MXC_TZIC
		ldr \base, =avic_base
		ldr \base, [\base]
		#ifdef CONFIG_MXC_IRQ_PRIOR
		ldr r4, [\base, #AVIC_NIMASK]
		#endif
		#elif defined CONFIG_MXC_TZIC
		ldr \base, =tzic_base
		ldr \base, [\base]
		#endif /* CONFIG_MXC_TZIC */
		.endm

		.macro arch_ret_to_user, tmp1, tmp2
		@@ -32,6 +37,7 @@
		@ and returns its number in irqnr
		@ and returns if an interrupt occured in irqstat
		.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
		#ifndef CONFIG_MXC_TZIC
		@ Load offset & priority of the highest priority
		@ interrupt pending from AVIC_NIVECSR
		ldr \irqstat, [\base, #0x40]
		@@ -44,6 +50,32 @@
		bicne \tmp, \irqstat, #0xFFFFFFE0
		strne \tmp, [\base, #AVIC_NIMASK]
		streq r4, [\base, #AVIC_NIMASK]
		#endif
		#elif defined CONFIG_MXC_TZIC
		@ Load offset & priority of the highest priority
		@ interrupt pending.
		@ 0xD80 is HIPND0 register
		mov \irqnr, #0
		mov \irqstat, #0x0D80
		1000:
		ldr \tmp, [\irqstat, \base]
		cmp \tmp, #0
		bne 1001f
		addeq \irqnr, \irqnr, #32
		addeq \irqstat, \irqstat, #4
		cmp \irqnr, #128
		blo 1000b
		b 2001f
		1001: mov \irqstat, #1
		1002: tst \tmp, \irqstat
		bne 2002f
		movs \tmp, \tmp, lsr #1
		addne \irqnr, \irqnr, #1
		bne 1002b
		2001:
		mov \irqnr, #0
		2002:
		movs \irqnr, \irqnr
		#endif
		.endm

+5 −1

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		@@ -12,9 +12,13 @@
		#define __ASM_ARCH_MXC_IRQS_H__

		/*
		* So far all i.MX SoCs have 64 internal interrupts
		* SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
		*/
		#ifdef CONFIG_MXC_TZIC
		#define MXC_INTERNAL_IRQS 128
		#else
		#define MXC_INTERNAL_IRQS 64
		#endif

		#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS