Commit a00024b0 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/cik: stop page faults from hanging the system (v2) 



Redirect invalid memory accesses to the default page
instead of locking up the memory controller.

v2: rebase on top of 2 level PTs

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1c49165d

drivers/gpu/drm/radeon/cik.c

+13 −2
Original line number Diff line number Diff line
@@ -1608,9 +1608,20 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) 
	/* enable context1-15 */

	WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,

	       (u32)(rdev->dummy_page.addr >> 12));

	WREG32(VM_CONTEXT1_CNTL2, 0);

	WREG32(VM_CONTEXT1_CNTL2, 4);

	WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);

				RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |

				PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |

				PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |

				VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |

				VALID_PROTECTION_FAULT_ENABLE_DEFAULT |

				READ_PROTECTION_FAULT_ENABLE_INTERRUPT |

				READ_PROTECTION_FAULT_ENABLE_DEFAULT |

				WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);



	/* TC cache setup ??? */

	WREG32(TC_CFG_L1_LOAD_POLICY0, 0);

drivers/gpu/drm/radeon/cikd.h

+11 −0
Original line number Diff line number Diff line
@@ -68,7 +68,18 @@ 
#define VM_CONTEXT0_CNTL				0x1410

#define		ENABLE_CONTEXT					(1 << 0)

#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)

#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)

#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)

#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)

#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)

#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)

#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)

#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)

#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)

#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)

#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)

#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)

#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)

#define VM_CONTEXT1_CNTL				0x1414

#define VM_CONTEXT0_CNTL2				0x1430

#define VM_CONTEXT1_CNTL2				0x1434

CRA Git | Maintained and supported by SUSTech CRA and CCSE