Merge tag 'tegra-for-5.8-media' of... (9ffc30a6) · Commits · 戴 / test

Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt

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		Binding for NVIDIA Tegra20 CPUFreq
		==================================

		Required properties:
		- clocks: Must contain an entry for the CPU clock.
		See ../clocks/clock-bindings.txt for details.
		- operating-points-v2: See ../bindings/opp/opp.txt for details.
		- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.

		For each opp entry in 'operating-points-v2' table:
		- opp-supported-hw: Two bitfields indicating:
		On Tegra20:
		1. CPU process ID mask
		2. SoC speedo ID mask

		On Tegra30:
		1. CPU process ID mask
		2. CPU speedo ID mask

		A bitwise AND is performed against these values and if any bit
		matches, the OPP gets enabled.

		- opp-microvolt: CPU voltage triplet.

		Optional properties:
		- cpu-supply: Phandle to the CPU power supply.

		Example:
		regulators {
		cpu_reg: regulator0 {
		regulator-name = "vdd_cpu";
		};
		};

		cpu0_opp_table: opp_table0 {
		compatible = "operating-points-v2";

		opp@456000000 {
		clock-latency-ns = <125000>;
		opp-microvolt = <825000 825000 1125000>;
		opp-supported-hw = <0x03 0x0001>;
		opp-hz = /bits/ 64 <456000000>;
		};

		...
		};

		cpus {
		cpu@0 {
		compatible = "arm,cortex-a9";
		clocks = <&tegra_car TEGRA20_CLK_CCLK>;
		operating-points-v2 = <&cpu0_opp_table>;
		cpu-supply = <&cpu_reg>;
		#cooling-cells = <2>;
		};
		};

Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt

+60 −13

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		@@ -40,14 +40,30 @@ of the following host1x client modules:

		Required properties:
		- compatible: "nvidia,tegra<chip>-vi"
		- reg: Physical base address and length of the controller's registers.
		- reg: Physical base address and length of the controller registers.
		- interrupts: The interrupt outputs from the controller.
		- clocks: Must contain one entry, for the module clock.
		- clocks: clocks: Must contain one entry, for the module clock.
		See ../clocks/clock-bindings.txt for details.
		- Tegra20/Tegra30/Tegra114/Tegra124:
		- resets: Must contain an entry for each entry in reset-names.
		See ../reset/reset.txt for details.
		- reset-names: Must include the following entries:
		- vi
		- Tegra210:
		- power-domains: Must include venc powergate node as vi is in VE partition.
		- Tegra210 has CSI part of VI sharing same host interface and register space.
		So, VI device node should have CSI child node.

		- csi: mipi csi interface to vi

		Required properties:
		- compatible: "nvidia,tegra210-csi"
		- reg: Physical base address offset to parent and length of the controller
		registers.
		- clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
		See ../clocks/clock-bindings.txt for details.
		- power-domains: Must include sor powergate node as csicil is in
		SOR partition.

		- epp: encoder pre-processor

		@@ -309,13 +325,44 @@ Example:
		reset-names = "mpe";
		};

		vi {
		compatible = "nvidia,tegra20-vi";
		reg = <0x54080000 0x00040000>;
		interrupts = <0 69 0x04>;
		clocks = <&tegra_car TEGRA20_CLK_VI>;
		resets = <&tegra_car 100>;
		reset-names = "vi";
		vi@54080000 {
		compatible = "nvidia,tegra210-vi";
		reg = <0x0 0x54080000 0x0 0x700>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;

		clocks = <&tegra_car TEGRA210_CLK_VI>;
		power-domains = <&pd_venc>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x0 0x0 0x54080000 0x2000>;

		csi@838 {
		compatible = "nvidia,tegra210-csi";
		reg = <0x838 0x1300>;
		assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
		<&tegra_car TEGRA210_CLK_CILCD>,
		<&tegra_car TEGRA210_CLK_CILE>,
		<&tegra_car TEGRA210_CLK_CSI_TPG>;
		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
		<&tegra_car TEGRA210_CLK_PLL_P>,
		<&tegra_car TEGRA210_CLK_PLL_P>;
		assigned-clock-rates = <102000000>,
		<102000000>,
		<102000000>,
		<972000000>;

		clocks = <&tegra_car TEGRA210_CLK_CSI>,
		<&tegra_car TEGRA210_CLK_CILAB>,
		<&tegra_car TEGRA210_CLK_CILCD>,
		<&tegra_car TEGRA210_CLK_CILE>,
		<&tegra_car TEGRA210_CLK_CSI_TPG>;
		clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
		power-domains = <&pd_sor>;
		};
		};

		epp {

Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt

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		@@ -35,6 +35,12 @@ Required properties:
		Due to above changes, Tegra114 I2C driver makes incompatible with
		previous hardware driver. Hence, tegra114 I2C controller is compatible
		with "nvidia,tegra114-i2c".
		nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
		host1x domain and typically used for camera use-cases. This VI I2C
		controller is mostly compatible with the programming model of the
		regular I2C controllers with a few exceptions. The I2C registers start
		at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
		(rather than 4) and the controller does not support slave mode.
		- reg: Should contain I2C controller registers physical address and length.
		- interrupts: Should contain I2C controller interrupts.
		- address-cells: Address cells for I2C device address.

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: NVIDIA Tegra210 SoC External Memory Controller

		maintainers:
		- Thierry Reding <thierry.reding@gmail.com>
		- Jon Hunter <jonathanh@nvidia.com>

		description: \|
		The EMC interfaces with the off-chip SDRAM to service the request stream
		sent from the memory controller.

		properties:
		compatible:
		const: nvidia,tegra210-emc

		reg:
		maxItems: 3

		clocks:
		items:
		- description: external memory clock

		clock-names:
		items:
		- const: emc

		interrupts:
		items:
		- description: EMC general interrupt

		memory-region:
		$ref: /schemas/types.yaml#/definitions/phandle
		description:
		phandle to a reserved memory region describing the table of EMC
		frequencies trained by the firmware

		nvidia,memory-controller:
		$ref: /schemas/types.yaml#/definitions/phandle
		description:
		phandle of the memory controller node

		required:
		- compatible
		- reg
		- clocks
		- clock-names
		- nvidia,memory-controller

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/tegra210-car.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>

		reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		emc_table: emc-table@83400000 {
		compatible = "nvidia,tegra210-emc-table";
		reg = <0x83400000 0x10000>;
		};
		};

		external-memory-controller@7001b000 {
		compatible = "nvidia,tegra210-emc";
		reg = <0x7001b000 0x1000>,
		<0x7001e000 0x1000>,
		<0x7001f000 0x1000>;
		clocks = <&tegra_car TEGRA210_CLK_EMC>;
		clock-names = "emc";
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		memory-region = <&emc_table>;
		nvidia,memory-controller = <&mc>;
		};

MAINTAINERS

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		@@ -16598,6 +16598,16 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
		S: Supported
		F: drivers/spi/spi-tegra*

		TEGRA VIDEO DRIVER
		M: Thierry Reding <thierry.reding@gmail.com>
		M: Jonathan Hunter <jonathanh@nvidia.com>
		M: Sowjanya Komatineni <skomatineni@nvidia.com>
		L: linux-media@vger.kernel.org
		L: linux-tegra@vger.kernel.org
		S: Maintained
		F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
		F: drivers/staging/media/tegra-video/

		TEGRA XUSB PADCTL DRIVER
		M: JC Kuo <jckuo@nvidia.com>
		S: Supported

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