Commit 9fbfb06a authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini
Browse files

MIPS: KVM: Arrayify struct kvm_mips_tlb::tlb_lo* 



The values of the EntryLo0 and EntryLo1 registers for a TLB entry are
stored in separate members of struct kvm_mips_tlb called tlb_lo0 and
tlb_lo1 respectively. To allow future code which needs to manipulate
arbitrary EntryLo data in the TLB entry to be simpler and less
conditional, replace these members with an array of two elements.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent e922a4cb

arch/mips/include/asm/kvm_host.h

+5 −6
Original line number Diff line number Diff line
@@ -310,13 +310,13 @@ enum emulation_result { 


#define VPN2_MASK		0xffffe000

#define KVM_ENTRYHI_ASID	MIPS_ENTRYHI_ASID

#define TLB_IS_GLOBAL(x)	(((x).tlb_lo0 & MIPS3_PG_G) &&		\

				 ((x).tlb_lo1 & MIPS3_PG_G))

#define TLB_IS_GLOBAL(x)	(((x).tlb_lo[0] & MIPS3_PG_G) &&	\

				 ((x).tlb_lo[1] & MIPS3_PG_G))

#define TLB_VPN2(x)		((x).tlb_hi & VPN2_MASK)

#define TLB_ASID(x)		((x).tlb_hi & KVM_ENTRYHI_ASID)

#define TLB_IS_VALID(x, va)	(((va) & (1 << PAGE_SHIFT))		\

				 ? ((x).tlb_lo1 & MIPS3_PG_V)		\

				 : ((x).tlb_lo0 & MIPS3_PG_V))

				 ? ((x).tlb_lo[1] & MIPS3_PG_V)		\

				 : ((x).tlb_lo[0] & MIPS3_PG_V))

#define TLB_HI_VPN2_HIT(x, y)	((TLB_VPN2(x) & ~(x).tlb_mask) ==	\

				 ((y) & VPN2_MASK & ~(x).tlb_mask))

#define TLB_HI_ASID_HIT(x, y)	(TLB_IS_GLOBAL(x) ||			\
@@ -325,8 +325,7 @@ enum emulation_result { 
struct kvm_mips_tlb {

	long tlb_mask;

	long tlb_hi;

	long tlb_lo0;

	long tlb_lo1;

	long tlb_lo[2];

};



#define KVM_MIPS_FPU_FPU	0x1

arch/mips/kvm/emulate.c

+5 −5
Original line number Diff line number Diff line
@@ -833,8 +833,8 @@ enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu) 


	tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);

	tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);

	tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);

	tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);

	tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);

	tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);



	kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",

		  pc, index, kvm_read_c0_guest_entryhi(cop0),
@@ -866,8 +866,8 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) 


	tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);

	tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);

	tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);

	tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);

	tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);

	tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);



	kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",

		  pc, index, kvm_read_c0_guest_entryhi(cop0),
@@ -2592,7 +2592,7 @@ enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, 
			}

		} else {

			kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",

				  tlb->tlb_hi, tlb->tlb_lo0, tlb->tlb_lo1);

				  tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]);

			/*

			 * OK we have a Guest TLB entry, now inject it into the

			 * shadow host TLB

arch/mips/kvm/mmu.c

+11 −9
Original line number Diff line number Diff line
@@ -141,28 +141,30 @@ int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, 
		pfn0 = 0;

		pfn1 = 0;

	} else {

		if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo0)

		if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo[0])

					   >> PAGE_SHIFT) < 0)

			return -1;



		if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo1)

		if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo[1])

					   >> PAGE_SHIFT) < 0)

			return -1;



		pfn0 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo0)

					    >> PAGE_SHIFT];

		pfn1 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo1)

					    >> PAGE_SHIFT];

		pfn0 = kvm->arch.guest_pmap[

			mips3_tlbpfn_to_paddr(tlb->tlb_lo[0]) >> PAGE_SHIFT];

		pfn1 = kvm->arch.guest_pmap[

			mips3_tlbpfn_to_paddr(tlb->tlb_lo[1]) >> PAGE_SHIFT];

	}



	/* Get attributes from the Guest TLB */

	entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) |

		   (tlb->tlb_lo0 & MIPS3_PG_D) | (tlb->tlb_lo0 & MIPS3_PG_V);

		   (tlb->tlb_lo[0] & MIPS3_PG_D) |

		   (tlb->tlb_lo[0] & MIPS3_PG_V);

	entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) |

		   (tlb->tlb_lo1 & MIPS3_PG_D) | (tlb->tlb_lo1 & MIPS3_PG_V);

		   (tlb->tlb_lo[1] & MIPS3_PG_D) |

		   (tlb->tlb_lo[1] & MIPS3_PG_V);



	kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc,

		  tlb->tlb_lo0, tlb->tlb_lo1);

		  tlb->tlb_lo[0], tlb->tlb_lo[1]);



	preempt_disable();

	entryhi = (tlb->tlb_hi & VPN2_MASK) | (KVM_GUEST_KERNEL_MODE(vcpu) ?

arch/mips/kvm/tlb.c

+11 −10
Original line number Diff line number Diff line
@@ -86,18 +86,19 @@ void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu) 
	for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {

		tlb = vcpu->arch.guest_tlb[i];

		kvm_info("TLB%c%3d Hi 0x%08lx ",

			 (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',

			 (tlb.tlb_lo[0] | tlb.tlb_lo[1]) & MIPS3_PG_V

							? ' ' : '*',

			 i, tlb.tlb_hi);

		kvm_info("Lo0=0x%09llx %c%c attr %lx ",

			 (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo0),

			 (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',

			 (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',

			 (tlb.tlb_lo0 >> 3) & 7);

			 (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[0]),

			 (tlb.tlb_lo[0] & MIPS3_PG_D) ? 'D' : ' ',

			 (tlb.tlb_lo[0] & MIPS3_PG_G) ? 'G' : ' ',

			 (tlb.tlb_lo[0] >> 3) & 7);

		kvm_info("Lo1=0x%09llx %c%c attr %lx sz=%lx\n",

			 (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo1),

			 (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',

			 (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',

			 (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask);

			 (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[1]),

			 (tlb.tlb_lo[1] & MIPS3_PG_D) ? 'D' : ' ',

			 (tlb.tlb_lo[1] & MIPS3_PG_G) ? 'G' : ' ',

			 (tlb.tlb_lo[1] >> 3) & 7, tlb.tlb_mask);

	}

}

EXPORT_SYMBOL_GPL(kvm_mips_dump_guest_tlbs);
@@ -219,7 +220,7 @@ int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi) 
	}



	kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n",

		  __func__, entryhi, index, tlb[i].tlb_lo0, tlb[i].tlb_lo1);

		  __func__, entryhi, index, tlb[i].tlb_lo[0], tlb[i].tlb_lo[1]);



	return index;

}

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