Commit 9f880327 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.6-2020-02-05' of git://people.freedesktop.org/~agd5f/linux into drm-next 



amd-drm-next-5.6-2020-02-05:

amdgpu:
- EDC fixes for Arcturus
- GDDR6 memory training fixe
- Fix for reading gfx clockgating registers while in GFXOFF state
- i2c freq fixes
- Misc display fixes
- TLB invalidation fix when using semaphores
- VCN 2.5 instancing fixes
- Switch raven1 gfxoff to a blacklist
- Coreboot workaround for KV/KB
- Root cause dongle fixes for display and revert workaround
- Enable GPU reset for renoir and navi
- Navi overclocking fixes
- Fix up confusing warnings in display clock validation on raven

amdkfd:
- SDMA fix

radeon:
- Misc LUT fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200206035458.3894-1-alexander.deucher@amd.com
parents a345cc0d 58fe03d6

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -120,6 +120,7 @@ amdgpu-y += \ 
	amdgpu_rlc.o \

	gfx_v8_0.o \

	gfx_v9_0.o \

	gfx_v9_4.o \

	gfx_v10_0.o



# add async DMA block

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −0
Original line number Diff line number Diff line
@@ -1009,10 +1009,14 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 


#define AMDGPU_REGS_IDX       (1<<0)

#define AMDGPU_REGS_NO_KIQ    (1<<1)

#define AMDGPU_REGS_KIQ       (1<<2)



#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)



#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)

#define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ)



#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))

#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+1 −1
Original line number Diff line number Diff line
@@ -527,7 +527,7 @@ static int acp_set_powergating_state(void *handle, 
				     enum amd_powergating_state state)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	bool enable = state == AMD_PG_STATE_GATE ? true : false;

	bool enable = (state == AMD_PG_STATE_GATE);



	if (adev->powerplay.pp_funcs &&

		adev->powerplay.pp_funcs->set_powergating_by_smu)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+1 −0
Original line number Diff line number Diff line
@@ -2129,6 +2129,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem 
		return -ENOMEM;



	mutex_init(&(*mem)->lock);

	INIT_LIST_HEAD(&(*mem)->bo_va_list);

	(*mem)->bo = amdgpu_bo_ref(gws_bo);

	(*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;

	(*mem)->process_info = process_info;

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+122 −107
Original line number Diff line number Diff line
@@ -42,19 +42,12 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 
	[AMDGPU_HW_IP_VCN_JPEG]	=	1,

};



static int amdgpu_ctx_total_num_entities(void)

{

	unsigned i, num_entities = 0;



	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)

		num_entities += amdgpu_ctx_num_entities[i];



	return num_entities;

}



static int amdgpu_ctx_priority_permit(struct drm_file *filp,

				      enum drm_sched_priority priority)

{

	if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)

		return -EINVAL;



	/* NORMAL and below are accessible by everyone */

	if (priority <= DRM_SCHED_PRIORITY_NORMAL)

		return 0;
@@ -68,64 +61,24 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp, 
	return -EACCES;

}



static int amdgpu_ctx_init(struct amdgpu_device *adev,

			   enum drm_sched_priority priority,

			   struct drm_file *filp,

			   struct amdgpu_ctx *ctx)

static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, const u32 ring)

{

	unsigned num_entities = amdgpu_ctx_total_num_entities();

	unsigned i, j;

	struct amdgpu_device *adev = ctx->adev;

	struct amdgpu_ctx_entity *entity;

	struct drm_gpu_scheduler **scheds = NULL, *sched = NULL;

	unsigned num_scheds = 0;

	enum drm_sched_priority priority;

	int r;



	if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)

		return -EINVAL;



	r = amdgpu_ctx_priority_permit(filp, priority);

	if (r)

		return r;



	memset(ctx, 0, sizeof(*ctx));

	ctx->adev = adev;



	ctx->fences = kcalloc(amdgpu_sched_jobs * num_entities,

			      sizeof(struct dma_fence*), GFP_KERNEL);

	if (!ctx->fences)

		return -ENOMEM;



	ctx->entities[0] = kcalloc(num_entities,

				   sizeof(struct amdgpu_ctx_entity),

	entity = kcalloc(1, offsetof(typeof(*entity), fences[amdgpu_sched_jobs]),

			 GFP_KERNEL);

	if (!ctx->entities[0]) {

		r = -ENOMEM;

		goto error_free_fences;

	}



	for (i = 0; i < num_entities; ++i) {

		struct amdgpu_ctx_entity *entity = &ctx->entities[0][i];

	if (!entity)

		return  -ENOMEM;



	entity->sequence = 1;

		entity->fences = &ctx->fences[amdgpu_sched_jobs * i];

	}

	for (i = 1; i < AMDGPU_HW_IP_NUM; ++i)

		ctx->entities[i] = ctx->entities[i - 1] +

			amdgpu_ctx_num_entities[i - 1];



	kref_init(&ctx->refcount);

	spin_lock_init(&ctx->ring_lock);

	mutex_init(&ctx->lock);



	ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);

	ctx->reset_counter_query = ctx->reset_counter;

	ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);

	ctx->init_priority = priority;

	ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;



	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

		struct drm_gpu_scheduler **scheds;

		struct drm_gpu_scheduler *sched;

		unsigned num_scheds = 0;



		switch (i) {

	priority = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ?

				ctx->init_priority : ctx->override_priority;

	switch (hw_ip) {

		case AMDGPU_HW_IP_GFX:

			sched = &adev->gfx.gfx_ring[0].sched;

			scheds = &sched;
@@ -168,51 +121,88 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, 
			break;

	}



		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)

			r = drm_sched_entity_init(&ctx->entities[i][j].entity,

						  priority, scheds,

						  num_scheds, &ctx->guilty);

	r = drm_sched_entity_init(&entity->entity, priority, scheds, num_scheds,

				  &ctx->guilty);

	if (r)

			goto error_cleanup_entities;

	}

		goto error_free_entity;



	ctx->entities[hw_ip][ring] = entity;

	return 0;



error_cleanup_entities:

	for (i = 0; i < num_entities; ++i)

		drm_sched_entity_destroy(&ctx->entities[0][i].entity);

	kfree(ctx->entities[0]);

error_free_entity:

	kfree(entity);



error_free_fences:

	kfree(ctx->fences);

	ctx->fences = NULL;

	return r;

}



static int amdgpu_ctx_init(struct amdgpu_device *adev,

			   enum drm_sched_priority priority,

			   struct drm_file *filp,

			   struct amdgpu_ctx *ctx)

{

	int r;



	r = amdgpu_ctx_priority_permit(filp, priority);

	if (r)

		return r;



	memset(ctx, 0, sizeof(*ctx));



	ctx->adev = adev;



	kref_init(&ctx->refcount);

	spin_lock_init(&ctx->ring_lock);

	mutex_init(&ctx->lock);



	ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);

	ctx->reset_counter_query = ctx->reset_counter;

	ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);

	ctx->init_priority = priority;

	ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;



	return 0;



}



static void amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity)

{



	int i;



	if (!entity)

		return;



	for (i = 0; i < amdgpu_sched_jobs; ++i)

		dma_fence_put(entity->fences[i]);



	kfree(entity);

}



static void amdgpu_ctx_fini(struct kref *ref)

{

	struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount);

	unsigned num_entities = amdgpu_ctx_total_num_entities();

	struct amdgpu_device *adev = ctx->adev;

	unsigned i, j;



	if (!adev)

		return;



	for (i = 0; i < num_entities; ++i)

		for (j = 0; j < amdgpu_sched_jobs; ++j)

			dma_fence_put(ctx->entities[0][i].fences[j]);

	kfree(ctx->fences);

	kfree(ctx->entities[0]);

	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

		for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) {

			amdgpu_ctx_fini_entity(ctx->entities[i][j]);

			ctx->entities[i][j] = NULL;

		}

	}



	mutex_destroy(&ctx->lock);



	kfree(ctx);

}



int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,

			  u32 ring, struct drm_sched_entity **entity)

{

	int r;



	if (hw_ip >= AMDGPU_HW_IP_NUM) {

		DRM_ERROR("unknown HW IP type: %d\n", hw_ip);

		return -EINVAL;
@@ -229,7 +219,13 @@ int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 
		return -EINVAL;

	}



	*entity = &ctx->entities[hw_ip][ring].entity;

	if (ctx->entities[hw_ip][ring] == NULL) {

		r = amdgpu_ctx_init_entity(ctx, hw_ip, ring);

		if (r)

			return r;

	}



	*entity = &ctx->entities[hw_ip][ring]->entity;

	return 0;

}
@@ -269,14 +265,17 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 
static void amdgpu_ctx_do_release(struct kref *ref)

{

	struct amdgpu_ctx *ctx;

	unsigned num_entities;

	u32 i;

	u32 i, j;



	ctx = container_of(ref, struct amdgpu_ctx, refcount);

	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {

			if (!ctx->entities[i][j])

				continue;



	num_entities = amdgpu_ctx_total_num_entities();

	for (i = 0; i < num_entities; i++)

		drm_sched_entity_destroy(&ctx->entities[0][i].entity);

			drm_sched_entity_destroy(&ctx->entities[i][j]->entity);

		}

	}



	amdgpu_ctx_fini(ref);

}
@@ -506,21 +505,25 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 
void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,

				  enum drm_sched_priority priority)

{

	unsigned num_entities = amdgpu_ctx_total_num_entities();

	enum drm_sched_priority ctx_prio;

	unsigned i;

	unsigned i, j;



	ctx->override_priority = priority;



	ctx_prio = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ?

			ctx->init_priority : ctx->override_priority;

	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {

			struct drm_sched_entity *entity;



	for (i = 0; i < num_entities; i++) {

		struct drm_sched_entity *entity = &ctx->entities[0][i].entity;

			if (!ctx->entities[i][j])

				continue;



			entity = &ctx->entities[i][j]->entity;

			drm_sched_entity_set_priority(entity, ctx_prio);

		}

	}

}



int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,

			       struct drm_sched_entity *entity)
@@ -554,32 +557,35 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) 


long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout)

{

	unsigned num_entities = amdgpu_ctx_total_num_entities();

	struct amdgpu_ctx *ctx;

	struct idr *idp;

	uint32_t id, i;

	uint32_t id, i, j;



	idp = &mgr->ctx_handles;



	mutex_lock(&mgr->lock);

	idr_for_each_entry(idp, ctx, id) {

		for (i = 0; i < num_entities; i++) {

		for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

			for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {

				struct drm_sched_entity *entity;



			entity = &ctx->entities[0][i].entity;

				if (!ctx->entities[i][j])

					continue;



				entity = &ctx->entities[i][j]->entity;

				timeout = drm_sched_entity_flush(entity, timeout);

			}

		}

	}

	mutex_unlock(&mgr->lock);

	return timeout;

}



void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)

{

	unsigned num_entities = amdgpu_ctx_total_num_entities();

	struct amdgpu_ctx *ctx;

	struct idr *idp;

	uint32_t id, i;

	uint32_t id, i, j;



	idp = &mgr->ctx_handles;
@@ -589,8 +595,17 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 
			continue;

		}



		for (i = 0; i < num_entities; i++)

			drm_sched_entity_fini(&ctx->entities[0][i].entity);

		for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

			for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {

				struct drm_sched_entity *entity;



				if (!ctx->entities[i][j])

					continue;



				entity = &ctx->entities[i][j]->entity;

				drm_sched_entity_fini(entity);

			}

		}

	}

}

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