Commit 9f58c93e authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge tag 'perf-core-for-mingo-5.5-20191203' of... 

Merge tag 'perf-core-for-mingo-5.5-20191203' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

 into perf/urgent

Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo:

perf report/top:

  - Fix segfault due to missing initialization of recently introduced
    struct map_symbol 'maps' field in append_inlines(), when running
    with DWARF callchains.

perf stat:

  Andi Kleen:

  - Affinity based optimizations for sessions with many events in
    machines with large core counts, avoiding excessive number of IPIs.

libtraceevent:

  - Sudip Mukherjee:

  - Fix installation with O=.

  - Copy pkg-config file to output folder when using O=.

perf bench:

  Arnaldo Carvalho de Melo:

  - Update the copies of x86's mem{cpy,set}_64.S, and because that
    now uses new stuff in linux/linkage.h, update that header too, which
    made the minimal clang version to build perf to be 3.5, as
    3.4 as found in some of the container images used to test build perf
    can't grok STT_FUNC as a token in .type lines.

ABI headers:

  Arnaldo Carvalho de Melo:

  - Sync x86's msr-index.h copy with the kernel sources, resulting
    in new MSRs to be usable in filter expressions in 'perf trace',
    such as IA32_TSX_CTRL.

  - Sync linux/fscrypt.h, linux/stat.h, sched.h and the kvm headers.

perf trace:

  Arnaldo Carvalho de Melo:

  - Add CLEAR_SIGHAND support for clone's flags arg

perf kvm:

  Arnaldo Carvalho de Melo:

  - Clarify the 'perf kvm' -i and -o command line options

perf test:

  Ian Rogers:

  - Move test functionality in to a 'perf test' entry.

Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 596cf45c 15b3904f

tools/arch/arm/include/uapi/asm/kvm.h

+2 −1
Original line number Diff line number Diff line
@@ -131,8 +131,9 @@ struct kvm_vcpu_events { 
	struct {

		__u8 serror_pending;

		__u8 serror_has_esr;

		__u8 ext_dabt_pending;

		/* Align it to 8 bytes */

		__u8 pad[6];

		__u8 pad[5];

		__u64 serror_esr;

	} exception;

	__u32 reserved[12];

tools/arch/arm64/include/uapi/asm/kvm.h

+4 −1
Original line number Diff line number Diff line
@@ -164,8 +164,9 @@ struct kvm_vcpu_events { 
	struct {

		__u8 serror_pending;

		__u8 serror_has_esr;

		__u8 ext_dabt_pending;

		/* Align it to 8 bytes */

		__u8 pad[6];

		__u8 pad[5];

		__u64 serror_esr;

	} exception;

	__u32 reserved[12];
@@ -323,6 +324,8 @@ struct kvm_vcpu_events { 
#define KVM_ARM_VCPU_TIMER_CTRL		1

#define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0

#define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1

#define KVM_ARM_VCPU_PVTIME_CTRL	2

#define   KVM_ARM_VCPU_PVTIME_IPA	0



/* KVM_IRQ_LINE irq field index values */

#define KVM_ARM_IRQ_VCPU2_SHIFT		28

tools/arch/powerpc/include/uapi/asm/kvm.h

+3 −0
Original line number Diff line number Diff line
@@ -667,6 +667,8 @@ struct kvm_ppc_cpu_char { 


/* PPC64 eXternal Interrupt Controller Specification */

#define KVM_DEV_XICS_GRP_SOURCES	1	/* 64-bit source attributes */

#define KVM_DEV_XICS_GRP_CTRL		2

#define   KVM_DEV_XICS_NR_SERVERS	1



/* Layout of 64-bit source attribute values */

#define  KVM_XICS_DESTINATION_SHIFT	0
@@ -683,6 +685,7 @@ struct kvm_ppc_cpu_char { 
#define KVM_DEV_XIVE_GRP_CTRL		1

#define   KVM_DEV_XIVE_RESET		1

#define   KVM_DEV_XIVE_EQ_SYNC		2

#define   KVM_DEV_XIVE_NR_SERVERS	3

#define KVM_DEV_XIVE_GRP_SOURCE		2	/* 64-bit source identifier */

#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG	3	/* 64-bit source identifier */

#define KVM_DEV_XIVE_GRP_EQ_CONFIG	4	/* 64-bit EQ identifier */

tools/arch/x86/include/asm/cpufeatures.h

+3 −0
Original line number Diff line number Diff line
@@ -292,6 +292,7 @@ 
#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */

#define X86_FEATURE_RDPRU		(13*32+ 4) /* Read processor register at user level */

#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */

#define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */

#define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
@@ -399,5 +400,7 @@ 
#define X86_BUG_MDS			X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */

#define X86_BUG_MSBDS_ONLY		X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */

#define X86_BUG_SWAPGS			X86_BUG(21) /* CPU is affected by speculation through SWAPGS */

#define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */

#define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */



#endif /* _ASM_X86_CPUFEATURES_H */

tools/arch/x86/include/asm/msr-index.h

+18 −0
Original line number Diff line number Diff line
@@ -93,6 +93,18 @@ 
						  * Microarchitectural Data

						  * Sampling (MDS) vulnerabilities.

						  */

#define ARCH_CAP_PSCHANGE_MC_NO		BIT(6)	 /*

						  * The processor is not susceptible to a

						  * machine check error due to modifying the

						  * code page size along with either the

						  * physical address or cache type

						  * without TLB invalidation.

						  */

#define ARCH_CAP_TSX_CTRL_MSR		BIT(7)	/* MSR for TSX control is available. */

#define ARCH_CAP_TAA_NO			BIT(8)	/*

						 * Not susceptible to

						 * TSX Async Abort (TAA) vulnerabilities.

						 */



#define MSR_IA32_FLUSH_CMD		0x0000010b

#define L1D_FLUSH			BIT(0)	/*
@@ -103,6 +115,10 @@ 
#define MSR_IA32_BBL_CR_CTL		0x00000119

#define MSR_IA32_BBL_CR_CTL3		0x0000011e



#define MSR_IA32_TSX_CTRL		0x00000122

#define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */

#define TSX_CTRL_CPUID_CLEAR		BIT(1)	/* Disable TSX enumeration */



#define MSR_IA32_SYSENTER_CS		0x00000174

#define MSR_IA32_SYSENTER_ESP		0x00000175

#define MSR_IA32_SYSENTER_EIP		0x00000176
@@ -393,6 +409,8 @@ 
#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064

#define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140

#define MSR_AMD64_OSVW_STATUS		0xc0010141

#define MSR_AMD_PPIN_CTL		0xc00102f0

#define MSR_AMD_PPIN			0xc00102f1

#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_DC_CFG		0xc0011022

#define MSR_AMD64_BU_CFG2		0xc001102a

CRA Git | Maintained and supported by SUSTech CRA and CCSE