Commit 9f443bf5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-next 

A few more fixes and cleanups for 4.6:
- DCE code cleanups
- HDP flush/invalidation fixes
- GPUVM fixes
- switch to drm_vblank_[on|off]
- PX fixes
- misc bug fixes

* 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: (50 commits)
  drm/amdgpu: split pipeline sync out of SDMA vm_flush() as well
  drm/amdgpu: Revert "add mutex for ba_va->valids/invalids"
  drm/amdgpu: Revert "add lock for interval tree in vm"
  drm/amdgpu: Revert "add spin lock to protect freed list in vm (v3)"
  drm/amdgpu: reserve the PD during unmap and remove
  drm/amdgpu: Fix two bugs in amdgpu_vm_bo_split_mapping
  drm/radeon: Don't drop DP 2.7 Ghz link setup on some cards.
  MAINTAINERS: update radeon entry to include amdgpu as well
  drm/amdgpu: disable runtime pm on PX laptops without dGPU power control
  drm/radeon: disable runtime pm on PX laptops without dGPU power control
  drm/amd/amdgpu: Fix indentation in do_set_base() (DCEv8)
  drm/amd/amdgpu: make afmt_init cleanup if alloc fails (DCEv8)
  drm/amd/amdgpu: Move config init flag to bottom of sw_init (DCEv8)
  drm/amd/amdgpu: Don't proceed into audio_fini if audio is disabled (DCEv8)
  drm/amd/amdgpu: Fix identation in do_set_base() (DCEv10)
  drm/amd/amdgpu: Make afmt_init cleanup if alloc fails (DCEv10)
  drm/amd/amdgpu: Move initialized flag to bottom of sw_init (DCEv10)
  drm/amd/amdgpu: Don't proceed in audio_fini if disabled (DCEv10)
  drm/amd/amdgpu: Fix indentation in dce_v11_0_crtc_do_set_base()
  drm/amd/amdgpu: Make afmt_init() cleanup if alloc fails (DCEv11)
  ...
parents 70a09f36 00b7c4ff

MAINTAINERS

+3 −1
Original line number Diff line number Diff line
@@ -3710,7 +3710,7 @@ F: drivers/gpu/vga/ 
F:	include/drm/

F:	include/uapi/drm/



RADEON DRM DRIVERS

RADEON and AMDGPU DRM DRIVERS

M:	Alex Deucher <alexander.deucher@amd.com>

M:	Christian König <christian.koenig@amd.com>

L:	dri-devel@lists.freedesktop.org
@@ -3718,6 +3718,8 @@ T: git git://people.freedesktop.org/~agd5f/linux 
S:	Supported

F:	drivers/gpu/drm/radeon/

F:	include/uapi/drm/radeon*

F:	drivers/gpu/drm/amd/

F:	include/uapi/drm/amdgpu*



DRM PANEL DRIVERS

M:	Thierry Reding <thierry.reding@gmail.com>

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+27 −14
Original line number Diff line number Diff line
@@ -287,9 +287,11 @@ struct amdgpu_ring_funcs { 
			struct amdgpu_ib *ib);

	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,

			   uint64_t seq, unsigned flags);

	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);

	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,

			      uint64_t pd_addr);

	void (*emit_hdp_flush)(struct amdgpu_ring *ring);

	void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);

	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,

				uint32_t gds_base, uint32_t gds_size,

				uint32_t gws_base, uint32_t gws_size,
@@ -369,9 +371,6 @@ struct amdgpu_fence { 
	struct amdgpu_ring		*ring;

	uint64_t			seq;



	/* filp or special value for fence creator */

	void				*owner;



	wait_queue_t			fence_wake;

};
@@ -392,8 +391,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 
				   unsigned irq_type);

void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);

void amdgpu_fence_driver_resume(struct amdgpu_device *adev);

int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,

		      struct amdgpu_fence **fence);

int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);

void amdgpu_fence_process(struct amdgpu_ring *ring);

int amdgpu_fence_wait_next(struct amdgpu_ring *ring);

int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
@@ -434,6 +432,8 @@ struct amdgpu_bo_list_entry { 
	struct ttm_validate_buffer	tv;

	struct amdgpu_bo_va		*bo_va;

	uint32_t			priority;

	struct page			**user_pages;

	int				user_invalidated;

};



struct amdgpu_bo_va_mapping {
@@ -445,7 +445,6 @@ struct amdgpu_bo_va_mapping { 


/* bo virtual addresses in a specific vm */

struct amdgpu_bo_va {

	struct mutex		        mutex;

	/* protected by bo being reserved */

	struct list_head		bo_list;

	struct fence		        *last_pt_update;
@@ -596,6 +595,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, 
struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);

int amdgpu_sync_wait(struct amdgpu_sync *sync);

void amdgpu_sync_free(struct amdgpu_sync *sync);

int amdgpu_sync_init(void);

void amdgpu_sync_fini(void);



/*

 * GART structures, functions & helpers
@@ -726,7 +727,7 @@ struct amdgpu_ib { 
	uint32_t			length_dw;

	uint64_t			gpu_addr;

	uint32_t			*ptr;

	struct amdgpu_fence		*fence;

	struct fence			*fence;

	struct amdgpu_user_fence        *user;

	struct amdgpu_vm		*vm;

	unsigned			vm_id;
@@ -845,7 +846,6 @@ struct amdgpu_vm_id { 


struct amdgpu_vm {

	/* tree of virtual addresses mapped */

	spinlock_t		it_lock;

	struct rb_root		va;



	/* protecting invalidated */
@@ -882,6 +882,13 @@ struct amdgpu_vm_manager_id { 
	struct list_head	list;

	struct fence		*active;

	atomic_long_t		owner;



	uint32_t		gds_base;

	uint32_t		gds_size;

	uint32_t		gws_base;

	uint32_t		gws_size;

	uint32_t		oa_base;

	uint32_t		oa_size;

};



struct amdgpu_vm_manager {
@@ -917,8 +924,11 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 
		      struct amdgpu_sync *sync, struct fence *fence,

		      unsigned *vm_id, uint64_t *vm_pd_addr);

void amdgpu_vm_flush(struct amdgpu_ring *ring,

		     unsigned vmid,

		     uint64_t pd_addr);

		     unsigned vm_id, uint64_t pd_addr,

		     uint32_t gds_base, uint32_t gds_size,

		     uint32_t gws_base, uint32_t gws_size,

		     uint32_t oa_base, uint32_t oa_size);

void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);

uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);

int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,

				    struct amdgpu_vm *vm);
@@ -1006,7 +1016,7 @@ struct amdgpu_bo_list { 
	struct amdgpu_bo *gds_obj;

	struct amdgpu_bo *gws_obj;

	struct amdgpu_bo *oa_obj;

	bool has_userptr;

	unsigned first_userptr;

	unsigned num_entries;

	struct amdgpu_bo_list_entry *array;

};
@@ -1135,8 +1145,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 
		  unsigned size, struct amdgpu_ib *ib);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,

		       struct amdgpu_ib *ib, void *owner,

		       struct fence *last_vm_update,

		       struct amdgpu_ib *ib, struct fence *last_vm_update,

		       struct fence **f);

int amdgpu_ib_pool_init(struct amdgpu_device *adev);

void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
@@ -2012,7 +2021,6 @@ struct amdgpu_device { 
	struct amdgpu_sdma		sdma;



	/* uvd */

	bool				has_uvd;

	struct amdgpu_uvd		uvd;



	/* vce */
@@ -2186,10 +2194,12 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))

#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))

#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))

#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))

#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))

#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))

#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))

#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))

#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))

#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))

#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))

#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
@@ -2314,12 +2324,15 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 
		       struct amdgpu_ring **out_ring);

void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);

bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);

int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);

int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,

				     uint32_t flags);

bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);

struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);

bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,

				  unsigned long end);

bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,

				       int *last_invalidated);

bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);

uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,

				 struct ttm_mem_reg *mem);

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

+4 −4
Original line number Diff line number Diff line
@@ -63,6 +63,10 @@ bool amdgpu_has_atpx(void) { 
	return amdgpu_atpx_priv.atpx_detected;

}



bool amdgpu_has_atpx_dgpu_power_cntl(void) {

	return amdgpu_atpx_priv.atpx.functions.power_cntl;

}



/**

 * amdgpu_atpx_call - call an ATPX method

 *
@@ -142,10 +146,6 @@ static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mas 
 */

static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)

{

	/* make sure required functions are enabled */

	/* dGPU power control is required */

	atpx->functions.power_cntl = true;



	if (atpx->functions.px_params) {

		union acpi_object *info;

		struct atpx_px_params output;

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

+16 −9
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, 
	struct amdgpu_bo *gws_obj = adev->gds.gws_gfx_bo;

	struct amdgpu_bo *oa_obj = adev->gds.oa_gfx_bo;



	bool has_userptr = false;

	unsigned last_entry = 0, first_userptr = num_entries;

	unsigned i;

	int r;
@@ -101,8 +101,9 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, 
	memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));



	for (i = 0; i < num_entries; ++i) {

		struct amdgpu_bo_list_entry *entry = &array[i];

		struct amdgpu_bo_list_entry *entry;

		struct drm_gem_object *gobj;

		struct amdgpu_bo *bo;

		struct mm_struct *usermm;



		gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
@@ -111,19 +112,24 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, 
			goto error_free;

		}



		entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));

		bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));

		drm_gem_object_unreference_unlocked(gobj);

		entry->priority = min(info[i].bo_priority,

				      AMDGPU_BO_LIST_MAX_PRIORITY);

		usermm = amdgpu_ttm_tt_get_usermm(entry->robj->tbo.ttm);



		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);

		if (usermm) {

			if (usermm != current->mm) {

				amdgpu_bo_unref(&entry->robj);

				amdgpu_bo_unref(&bo);

				r = -EPERM;

				goto error_free;

			}

			has_userptr = true;

			entry = &array[--first_userptr];

		} else {

			entry = &array[last_entry++];

		}



		entry->robj = bo;

		entry->priority = min(info[i].bo_priority,

				      AMDGPU_BO_LIST_MAX_PRIORITY);

		entry->tv.bo = &entry->robj->tbo;

		entry->tv.shared = true;
@@ -145,7 +151,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, 
	list->gds_obj = gds_obj;

	list->gws_obj = gws_obj;

	list->oa_obj = oa_obj;

	list->has_userptr = has_userptr;

	list->first_userptr = first_userptr;

	list->array = array;

	list->num_entries = num_entries;
@@ -194,6 +200,7 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 


		list_add_tail(&list->array[i].tv.head,

			      &bucket[priority]);

		list->array[i].user_pages = NULL;

	}



	/* Connect the sorted buckets in the output list. */

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+112 −5
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 
	p->uf_entry.priority = 0;

	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;

	p->uf_entry.tv.shared = true;

	p->uf_entry.user_pages = NULL;



	drm_gem_object_unreference_unlocked(gobj);

	return 0;
@@ -297,6 +298,7 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, 


	list_for_each_entry(lobj, validated, tv.head) {

		struct amdgpu_bo *bo = lobj->robj;

		bool binding_userptr = false;

		struct mm_struct *usermm;

		uint32_t domain;
@@ -304,6 +306,15 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, 
		if (usermm && usermm != current->mm)

			return -EPERM;



		/* Check if we have user pages and nobody bound the BO already */

		if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {

			size_t size = sizeof(struct page *);



			size *= bo->tbo.ttm->num_pages;

			memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);

			binding_userptr = true;

		}



		if (bo->pin_count)

			continue;
@@ -334,6 +345,11 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, 
			}

			return r;

		}



		if (binding_userptr) {

			drm_free_large(lobj->user_pages);

			lobj->user_pages = NULL;

		}

	}

	return 0;

}
@@ -342,15 +358,18 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
				union drm_amdgpu_cs *cs)

{

	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;

	struct amdgpu_bo_list_entry *e;

	struct list_head duplicates;

	bool need_mmap_lock = false;

	unsigned i, tries = 10;

	int r;



	INIT_LIST_HEAD(&p->validated);



	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);

	if (p->bo_list) {

		need_mmap_lock = p->bo_list->has_userptr;

		need_mmap_lock = p->bo_list->first_userptr !=

			p->bo_list->num_entries;

		amdgpu_bo_list_get_list(p->bo_list, &p->validated);

	}
@@ -363,9 +382,81 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
	if (need_mmap_lock)

		down_read(&current->mm->mmap_sem);



	r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);

	while (1) {

		struct list_head need_pages;

		unsigned i;



		r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,

					   &duplicates);

		if (unlikely(r != 0))

		goto error_reserve;

			goto error_free_pages;



		/* Without a BO list we don't have userptr BOs */

		if (!p->bo_list)

			break;



		INIT_LIST_HEAD(&need_pages);

		for (i = p->bo_list->first_userptr;

		     i < p->bo_list->num_entries; ++i) {



			e = &p->bo_list->array[i];



			if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,

				 &e->user_invalidated) && e->user_pages) {



				/* We acquired a page array, but somebody

				 * invalidated it. Free it an try again

				 */

				release_pages(e->user_pages,

					      e->robj->tbo.ttm->num_pages,

					      false);

				drm_free_large(e->user_pages);

				e->user_pages = NULL;

			}



			if (e->robj->tbo.ttm->state != tt_bound &&

			    !e->user_pages) {

				list_del(&e->tv.head);

				list_add(&e->tv.head, &need_pages);



				amdgpu_bo_unreserve(e->robj);

			}

		}



		if (list_empty(&need_pages))

			break;



		/* Unreserve everything again. */

		ttm_eu_backoff_reservation(&p->ticket, &p->validated);



		/* We tried to often, just abort */

		if (!--tries) {

			r = -EDEADLK;

			goto error_free_pages;

		}



		/* Fill the page arrays for all useptrs. */

		list_for_each_entry(e, &need_pages, tv.head) {

			struct ttm_tt *ttm = e->robj->tbo.ttm;



			e->user_pages = drm_calloc_large(ttm->num_pages,

							 sizeof(struct page*));

			if (!e->user_pages) {

				r = -ENOMEM;

				goto error_free_pages;

			}



			r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);

			if (r) {

				drm_free_large(e->user_pages);

				e->user_pages = NULL;

				goto error_free_pages;

			}

		}



		/* And try again. */

		list_splice(&need_pages, &p->validated);

	}



	amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
@@ -397,10 +488,26 @@ error_validate: 
		ttm_eu_backoff_reservation(&p->ticket, &p->validated);

	}



error_reserve:

error_free_pages:



	if (need_mmap_lock)

		up_read(&current->mm->mmap_sem);



	if (p->bo_list) {

		for (i = p->bo_list->first_userptr;

		     i < p->bo_list->num_entries; ++i) {

			e = &p->bo_list->array[i];



			if (!e->user_pages)

				continue;



			release_pages(e->user_pages,

				      e->robj->tbo.ttm->num_pages,

				      false);

			drm_free_large(e->user_pages);

		}

	}



	return r;

}

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