pwm: sun4i: Add support to output source clock directly (9f28e95b) · Commits · 戴 / test

drivers/pwm/pwm-sun4i.c

+46 −2

Original line number	Diff line number	Diff line
		@@ -3,6 +3,10 @@
		* Driver for Allwinner sun4i Pulse Width Modulation Controller
		*
		* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
		*
		* Limitations:
		* - When outputing the source clock directly, the PWM logic will be bypassed
		* and the currently running period is not guaranteed to be completed
		*/

		#include <linux/bitops.h>
		@@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {

		struct sun4i_pwm_data {
		bool has_prescaler_bypass;
		bool has_direct_mod_clk_output;
		unsigned int npwm;
		};

		@@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,

		val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

		/*
		* PWM chapter in H6 manual has a diagram which explains that if bypass
		* bit is set, no other setting has any meaning. Even more, experiment
		* proved that also enable bit is ignored in this case.
		*/
		if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
		sun4i_pwm->data->has_direct_mod_clk_output) {
		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
		state->polarity = PWM_POLARITY_NORMAL;
		state->enabled = true;
		return;
		}

		if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
		sun4i_pwm->data->has_prescaler_bypass)
		prescaler = 1;
		@@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,

		static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
		const struct pwm_state *state,
		u32 dty, u32 prd, unsigned int *prsclr)
		u32 dty, u32 prd, unsigned int *prsclr,
		bool *bypass)
		{
		u64 clk_rate, div = 0;
		unsigned int pval, prescaler = 0;

		clk_rate = clk_get_rate(sun4i_pwm->clk);

		*bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
		state->enabled &&
		(state->period * clk_rate >= NSEC_PER_SEC) &&
		(state->period * clk_rate < 2 * NSEC_PER_SEC) &&
		(state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);

		/* Skip calculation of other parameters if we bypass them */
		if (*bypass)
		return 0;

		if (sun4i_pwm->data->has_prescaler_bypass) {
		/* First, test without any prescaler when available */
		prescaler = PWM_PRESCAL_MASK;
		@@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
		int ret;
		unsigned int delay_us, prescaler;
		unsigned long now;
		bool bypass;

		pwm_get_state(pwm, &cstate);

		@@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
		spin_lock(&sun4i_pwm->ctrl_lock);
		ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

		ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
		ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
		&bypass);
		if (ret) {
		dev_err(chip->dev, "period exceeds the maximum value\n");
		spin_unlock(&sun4i_pwm->ctrl_lock);
		@@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
		return ret;
		}

		if (sun4i_pwm->data->has_direct_mod_clk_output) {
		if (bypass) {
		ctrl \|= BIT_CH(PWM_BYPASS, pwm->hwpwm);
		/* We can skip other parameter */
		sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
		spin_unlock(&sun4i_pwm->ctrl_lock);
		return 0;
		}

		ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
		}

		if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
		/* Prescaler changed, the clock has to be gated */
		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

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