Commit 9f21f379 authored Dec 30, 2019 by Alvin Lee Committed by Alex Deucher Jan 16, 2020

drm/amd/display: Enable double buffer for OTG_BLANK



[Why]
Currently if seamless boot is enabled, we will skip double buffer enable
for OTG_BLANK. However, we need the double buffer enable in order to
block global sync signals when OTG becomes blanked (for PSR). Blocking
global sync signals prevent pipe from requesting data.

[How]
Move tg_init before seamless boot check.

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 8547058b

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -1188,8 +1188,14 @@ void dcn10_init_pipes(struct dc dc, struct dc_state context)
		if (can_apply_seamless_boot &&
		pipe_ctx->stream != NULL &&
		pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
		pipe_ctx->stream_res.tg))
		pipe_ctx->stream_res.tg)) {
		// Enable double buffering for OTG_BLANK no matter if
		// seamless boot is enabled or not to suppress global sync
		// signals when OTG blanked. This is to prevent pipe from
		// requesting data while in PSR.
		tg->funcs->tg_init(tg);
		continue;
		}

		/* Disable on the current state so the new one isn't cleared. */
		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

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