Commit 9ee76098 authored by Wangyan Wang's avatar Wangyan Wang Committed by CK Hu
Browse files

drm/mediatek: no change parent rate in round_rate() for MT2701 hdmi phy 



This is the third step to make MT2701 HDMI stable.
We should not change the rate of parent for hdmi phy when
doing round_rate for this clock. The parent clock of hdmi
phy must be the same as it. We change it when doing set_rate
only.

Signed-off-by: default avatarWangyan Wang <wangyan.wang@mediatek.com>
Signed-off-by: default avatarCK Hu <ck.hu@mediatek.com>
parent 8eeb3946

drivers/gpu/drm/mediatek/mtk_hdmi_phy.c

+0 −14
Original line number Original line Diff line number Diff line
@@ -15,20 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = { 
	.owner = THIS_MODULE,

	.owner = THIS_MODULE,

};

};





long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,

			     unsigned long *parent_rate)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);



	hdmi_phy->pll_rate = rate;

	if (rate <= 74250000)

		*parent_rate = rate;

	else

		*parent_rate = rate / 2;



	return rate;

}



void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,

void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,

			     u32 bits)

			     u32 bits)

{

{

drivers/gpu/drm/mediatek/mtk_hdmi_phy.h

+0 −2
Original line number Original line Diff line number Diff line
@@ -49,8 +49,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, 
void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,

void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,

		       u32 val, u32 mask);

		       u32 val, u32 mask);

struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);

struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);

long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,

			     unsigned long *parent_rate);





extern struct platform_driver mtk_hdmi_phy_driver;

extern struct platform_driver mtk_hdmi_phy_driver;

extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;

extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;

drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -106,6 +106,12 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 
	usleep_range(80, 100);

	usleep_range(80, 100);

}

}





static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long *parent_rate)

{

	return rate;

}



static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,

static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,

				 unsigned long parent_rate)

				 unsigned long parent_rate)

{

{

drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c

+14 −0
Original line number Original line Diff line number Diff line
@@ -199,6 +199,20 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 
	usleep_range(100, 150);

	usleep_range(100, 150);

}

}





static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long *parent_rate)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);



	hdmi_phy->pll_rate = rate;

	if (rate <= 74250000)

		*parent_rate = rate;

	else

		*parent_rate = rate / 2;



	return rate;

}



static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,

static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,

				 unsigned long parent_rate)

				 unsigned long parent_rate)

{

{

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