Commit 9ed8b1f9 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: clean up vram/gtt location handling 



Add a per-asic MC (memory controller) mask which holds the
mak address mask the asic is capable of.  Use this when
calculating the vram and gtt locations rather using asic
specific functions or limiting everything to 32 bits.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 367cbe2f

drivers/gpu/drm/radeon/r600.c

+1 −1
Original line number Diff line number Diff line
@@ -1145,7 +1145,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc 
	}

	if (rdev->flags & RADEON_IS_AGP) {

		size_bf = mc->gtt_start;

		size_af = 0xFFFFFFFF - mc->gtt_end;

		size_af = mc->mc_mask - mc->gtt_end;

		if (size_bf > size_af) {

			if (mc->mc_vram_size > size_bf) {

				dev_warn(rdev->dev, "limiting VRAM\n");

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -517,6 +517,7 @@ struct radeon_mc { 
	bool			vram_is_ddr;

	bool			igp_sideport_enabled;

	u64                     gtt_base_align;

	u64                     mc_mask;

};



bool radeon_combios_sideport_present(struct radeon_device *rdev);

drivers/gpu/drm/radeon/radeon_device.c

+13 −2
Original line number Diff line number Diff line
@@ -359,7 +359,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 
	uint64_t limit = (uint64_t)radeon_vram_limit << 20;



	mc->vram_start = base;

	if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {

	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {

		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");

		mc->real_vram_size = mc->aper_size;

		mc->mc_vram_size = mc->aper_size;
@@ -394,7 +394,7 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 
{

	u64 size_af, size_bf;



	size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;

	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;

	size_bf = mc->vram_start & ~mc->gtt_base_align;

	if (size_bf > size_af) {

		if (mc->gtt_size > size_bf) {
@@ -1068,6 +1068,17 @@ int radeon_device_init(struct radeon_device *rdev, 
		radeon_agp_disable(rdev);

	}



	/* Set the internal MC address mask

	 * This is the max address of the GPU's

	 * internal address space.

	 */

	if (rdev->family >= CHIP_CAYMAN)

		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */

	else if (rdev->family >= CHIP_CEDAR)

		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */

	else

		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */



	/* set DMA mask + need_dma32 flags.

	 * PCIE - can handle 40-bits.

	 * IGP - can handle 40-bits

drivers/gpu/drm/radeon/rv770.c

+1 −1
Original line number Diff line number Diff line
@@ -840,7 +840,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 
	}

	if (rdev->flags & RADEON_IS_AGP) {

		size_bf = mc->gtt_start;

		size_af = 0xFFFFFFFF - mc->gtt_end;

		size_af = mc->mc_mask - mc->gtt_end;

		if (size_bf > size_af) {

			if (mc->mc_vram_size > size_bf) {

				dev_warn(rdev->dev, "limiting VRAM\n");

drivers/gpu/drm/radeon/si.c

+2 −42
Original line number Diff line number Diff line
@@ -2538,46 +2538,6 @@ static void si_mc_program(struct radeon_device *rdev) 
	rv515_vga_render_disable(rdev);

}



/* SI MC address space is 40 bits */

static void si_vram_location(struct radeon_device *rdev,

			     struct radeon_mc *mc, u64 base)

{

	mc->vram_start = base;

	if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {

		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");

		mc->real_vram_size = mc->aper_size;

		mc->mc_vram_size = mc->aper_size;

	}

	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;

	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",

			mc->mc_vram_size >> 20, mc->vram_start,

			mc->vram_end, mc->real_vram_size >> 20);

}



static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)

{

	u64 size_af, size_bf;



	size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;

	size_bf = mc->vram_start & ~mc->gtt_base_align;

	if (size_bf > size_af) {

		if (mc->gtt_size > size_bf) {

			dev_warn(rdev->dev, "limiting GTT\n");

			mc->gtt_size = size_bf;

		}

		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;

	} else {

		if (mc->gtt_size > size_af) {

			dev_warn(rdev->dev, "limiting GTT\n");

			mc->gtt_size = size_af;

		}

		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;

	}

	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;

	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",

			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);

}



static void si_vram_gtt_location(struct radeon_device *rdev,

				 struct radeon_mc *mc)

{
@@ -2587,9 +2547,9 @@ static void si_vram_gtt_location(struct radeon_device *rdev, 
		mc->real_vram_size = 0xFFC0000000ULL;

		mc->mc_vram_size = 0xFFC0000000ULL;

	}

	si_vram_location(rdev, &rdev->mc, 0);

	radeon_vram_location(rdev, &rdev->mc, 0);

	rdev->mc.gtt_base_align = 0;

	si_gtt_location(rdev, mc);

	radeon_gtt_location(rdev, mc);

}



static int si_mc_init(struct radeon_device *rdev)

CRA Git | Maintained and supported by SUSTech CRA and CCSE