Commit 9eae5e27 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915: prefer 3-letter acronym for ironlake 



We are currently using a mix of platform name and acronym to name the
functions. Let's prefer the acronym as it should be clear what platform
it's about and it's shorter, so it doesn't go over 80 columns in a few
cases. This converts ironlake to ilk where appropriate.

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191224084012.24241-7-lucas.demarchi@intel.com
parent 95be3484

drivers/gpu/drm/i915/display/intel_crt.c

+4 −4
Original line number Diff line number Diff line
@@ -247,7 +247,7 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder, 


	intel_ddi_disable_transcoder_func(old_crtc_state);



	ironlake_pfit_disable(old_crtc_state);

	ilk_pfit_disable(old_crtc_state);



	intel_ddi_disable_pipe_clock(old_crtc_state);
@@ -351,7 +351,7 @@ intel_crt_mode_valid(struct drm_connector *connector, 


	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */

	if (HAS_PCH_LPT(dev_priv) &&

	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))

	    ilk_get_lanes_required(mode->clock, 270000, 24) > 2)

		return MODE_CLOCK_HIGH;



	/* HSW/BDW FDI limited to 4k */
@@ -427,7 +427,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, 
	return 0;

}



static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)

static bool ilk_crt_detect_hotplug(struct drm_connector *connector)

{

	struct drm_device *dev = connector->dev;

	struct intel_crt *crt = intel_attached_crt(connector);
@@ -535,7 +535,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) 
	int i, tries = 0;



	if (HAS_PCH_SPLIT(dev_priv))

		return intel_ironlake_crt_detect_hotplug(connector);

		return ilk_crt_detect_hotplug(connector);



	if (IS_VALLEYVIEW(dev_priv))

		return valleyview_crt_detect_hotplug(connector);

drivers/gpu/drm/i915/display/intel_ddi.c

+1 −1
Original line number Diff line number Diff line
@@ -3916,7 +3916,7 @@ static void intel_ddi_post_disable(struct intel_encoder *encoder, 
	if (INTEL_GEN(dev_priv) >= 9)

		skl_scaler_disable(old_crtc_state);

	else

		ironlake_pfit_disable(old_crtc_state);

		ilk_pfit_disable(old_crtc_state);



	/*

	 * When called from DP MST code:

drivers/gpu/drm/i915/display/intel_display.c

+84 −84

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/display/intel_display.h

+2 −2
Original line number Diff line number Diff line
@@ -521,7 +521,7 @@ int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);

void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);



int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);

int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);

void vlv_wait_port_ready(struct drm_i915_private *dev_priv,

			 struct intel_digital_port *dport,

			 unsigned int expected_mask);
@@ -579,7 +579,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);

int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);

void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);

void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);

void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);

u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,

			const struct intel_plane_state *plane_state);

u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

+17 −17
Original line number Diff line number Diff line
@@ -2509,7 +2509,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
	 *

	 * CPT PCH is quite different, having many bits moved

	 * to the TRANS_DP_CTL register instead. That

	 * configuration happens (oddly) in ironlake_pch_enable

	 * configuration happens (oddly) in ilk_pch_enable

	 */



	/* Preserve the BIOS-computed detected bit. This is
@@ -2653,7 +2653,7 @@ static void edp_wait_backlight_off(struct intel_dp *intel_dp) 
 * is locked

 */



static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)

static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u32 control;
@@ -2703,7 +2703,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 
	if (!edp_have_panel_power(intel_dp))

		wait_panel_power_cycle(intel_dp);



	pp = ironlake_get_pp_control(intel_dp);

	pp = ilk_get_pp_control(intel_dp);

	pp |= EDP_FORCE_VDD;



	pp_stat_reg = _pp_stat_reg(intel_dp);
@@ -2768,7 +2768,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 
		      intel_dig_port->base.base.base.id,

		      intel_dig_port->base.base.name);



	pp = ironlake_get_pp_control(intel_dp);

	pp = ilk_get_pp_control(intel_dp);

	pp &= ~EDP_FORCE_VDD;



	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
@@ -2864,7 +2864,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) 
	wait_panel_power_cycle(intel_dp);



	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

	pp = ironlake_get_pp_control(intel_dp);

	pp = ilk_get_pp_control(intel_dp);

	if (IS_GEN(dev_priv, 5)) {

		/* ILK workaround: disable reset around power sequence */

		pp &= ~PANEL_POWER_RESET;
@@ -2919,7 +2919,7 @@ static void edp_panel_off(struct intel_dp *intel_dp) 
	WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",

	     dig_port->base.base.base.id, dig_port->base.base.name);



	pp = ironlake_get_pp_control(intel_dp);

	pp = ilk_get_pp_control(intel_dp);

	/* We need to switch off panel power _and_ force vdd, for otherwise some

	 * panels get very unhappy and cease to work. */

	pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
@@ -2968,7 +2968,7 @@ static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 
		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

		u32 pp;



		pp = ironlake_get_pp_control(intel_dp);

		pp = ilk_get_pp_control(intel_dp);

		pp |= EDP_BLC_ENABLE;



		I915_WRITE(pp_ctrl_reg, pp);
@@ -3004,7 +3004,7 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 
		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

		u32 pp;



		pp = ironlake_get_pp_control(intel_dp);

		pp = ilk_get_pp_control(intel_dp);

		pp &= ~EDP_BLC_ENABLE;



		I915_WRITE(pp_ctrl_reg, pp);
@@ -3042,7 +3042,7 @@ static void intel_edp_backlight_power(struct intel_connector *connector, 


	is_enabled = false;

	with_pps_lock(intel_dp, wakeref)

		is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;

		is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;

	if (is_enabled == enable)

		return;
@@ -3079,7 +3079,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)

#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)



static void ironlake_edp_pll_on(struct intel_dp *intel_dp,

static void ilk_edp_pll_on(struct intel_dp *intel_dp,

			   const struct intel_crtc_state *pipe_config)

{

	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -3119,7 +3119,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp, 
	udelay(200);

}



static void ironlake_edp_pll_off(struct intel_dp *intel_dp,

static void ilk_edp_pll_off(struct intel_dp *intel_dp,

			    const struct intel_crtc_state *old_crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
@@ -3410,7 +3410,7 @@ static void g4x_post_disable_dp(struct intel_encoder *encoder, 


	/* Only ilk+ has port A */

	if (port == PORT_A)

		ironlake_edp_pll_off(intel_dp, old_crtc_state);

		ilk_edp_pll_off(intel_dp, old_crtc_state);

}



static void vlv_post_disable_dp(struct intel_encoder *encoder,
@@ -3615,7 +3615,7 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder, 


	/* Only ilk+ has port A */

	if (port == PORT_A)

		ironlake_edp_pll_on(intel_dp, pipe_config);

		ilk_edp_pll_on(intel_dp, pipe_config);

}



static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
@@ -6693,7 +6693,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) 


	intel_pps_get_registers(intel_dp, &regs);



	pp_ctl = ironlake_get_pp_control(intel_dp);

	pp_ctl = ilk_get_pp_control(intel_dp);



	/* Ensure PPS is unlocked */

	if (!HAS_DDI(dev_priv))
@@ -6863,7 +6863,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, 
	 * soon as the new power sequencer gets initialized.

	 */

	if (force_disable_vdd) {

		u32 pp = ironlake_get_pp_control(intel_dp);

		u32 pp = ilk_get_pp_control(intel_dp);



		WARN(pp & PANEL_POWER_ON, "Panel power already on\n");

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