Commit 9eac6d0a authored by Lennert Buytenhek's avatar Lennert Buytenhek Committed by Nicolas Pitre
Browse files

ARM: Remove dependency of plat-orion GPIO code on mach directory includes. 



This patch makes the various mach dirs that use the plat-orion GPIO
code pass in GPIO-related platform info (GPIO controller base address,
secondary base IRQ number, etc) explicitly, instead of having
plat-orion get those values by including a mach dir include file --
the latter mechanism is problematic if you want to support multiple
ARM platforms in the same kernel image.

Signed-off-by: default avatarLennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: default avatarNicolas Pitre <nico@fluxnic.net>
parent 4ee1f6b5

arch/arm/mach-dove/include/mach/dove.h

+2 −1
Original line number Diff line number Diff line
@@ -130,7 +130,8 @@ 
#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)

#define DOVE_RESET_SAMPLE_LO	(DOVE_MPP_VIRT_BASE | 0x014)

#define DOVE_RESET_SAMPLE_HI	(DOVE_MPP_VIRT_BASE | 0x018)

#define DOVE_GPIO_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xd0400)

#define DOVE_GPIO_LO_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xd0400)

#define DOVE_GPIO_HI_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xd0420)

#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)

#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xe803c)

#define  DOVE_AU1_SPDIFO_GPIO_EN	(1 << 1)

arch/arm/mach-dove/include/mach/gpio.h

+0 −42
Original line number Diff line number Diff line
@@ -6,46 +6,4 @@ 
 * warranty of any kind, whether express or implied.

 */



#ifndef __ASM_ARCH_GPIO_H

#define __ASM_ARCH_GPIO_H



#include <asm/errno.h>

#include <mach/irqs.h>

#include <plat/gpio.h>
 
#include <asm-generic/gpio.h>		/* cansleep wrappers */



#define GPIO_MAX	72



#define GPIO_BASE_LO		(DOVE_GPIO_VIRT_BASE + 0x00)

#define GPIO_BASE_HI		(DOVE_GPIO_VIRT_BASE + 0x20)



#define GPIO_BASE(pin)		((pin < 32) ? GPIO_BASE_LO :		\

				 ((pin < 64) ? GPIO_BASE_HI :		\

				  DOVE_GPIO2_VIRT_BASE))



#define GPIO_OUT(pin)		(GPIO_BASE(pin) + 0x00)

#define GPIO_IO_CONF(pin)	(GPIO_BASE(pin) + 0x04)

#define GPIO_BLINK_EN(pin)	(GPIO_BASE(pin) + 0x08)

#define GPIO_IN_POL(pin)	(GPIO_BASE(pin) + 0x0c)

#define GPIO_DATA_IN(pin)	(GPIO_BASE(pin) + 0x10)

#define GPIO_EDGE_CAUSE(pin)	(GPIO_BASE(pin) + 0x14)

#define GPIO_EDGE_MASK(pin)	(GPIO_BASE(pin) + 0x18)

#define GPIO_LEVEL_MASK(pin)	(GPIO_BASE(pin) + 0x1c)



static inline int gpio_to_irq(int pin)

{

	if (pin < NR_GPIO_IRQS)

		return pin + IRQ_DOVE_GPIO_START;



	return -EINVAL;

}



static inline int irq_to_gpio(int irq)

{

	if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)

		return irq - IRQ_DOVE_GPIO_START;



	return -EINVAL;

}



#endif

arch/arm/mach-dove/irq.c

+14 −16
Original line number Diff line number Diff line
@@ -99,11 +99,21 @@ void __init dove_init_irq(void) 
	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));



	/*

	 * Mask and clear GPIO IRQ interrupts.

	 * Initialize gpiolib for GPIOs 0-71.

	 */

	writel(0, GPIO_LEVEL_MASK(0));

	writel(0, GPIO_EDGE_MASK(0));

	writel(0, GPIO_EDGE_CAUSE(0));

	orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START);

	set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);

	set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);

	set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);

	set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);



	orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START + 32);

	set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);



	orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START + 64);



	/*

	 * Mask and clear PMU interrupts
@@ -111,18 +121,6 @@ void __init dove_init_irq(void) 
	writel(0, PMU_INTERRUPT_MASK);

	writel(0, PMU_INTERRUPT_CAUSE);



	for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {

		set_irq_chip(i, &orion_gpio_irq_chip);

		set_irq_handler(i, handle_level_irq);

		irq_desc[i].status |= IRQ_LEVEL;

		set_irq_flags(i, IRQF_VALID);

	}

	set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);

	set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);

	set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);

	set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);

	set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);



	for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {

		set_irq_chip(i, &pmu_irq_chip);

		set_irq_handler(i, handle_level_irq);

arch/arm/mach-kirkwood/include/mach/gpio.h

+0 −29
Original line number Diff line number Diff line
@@ -6,33 +6,4 @@ 
 * warranty of any kind, whether express or implied.

 */



#ifndef __ASM_ARCH_GPIO_H

#define __ASM_ARCH_GPIO_H



#include <mach/irqs.h>

#include <plat/gpio.h>
 
#include <asm-generic/gpio.h>		/* cansleep wrappers */



#define GPIO_MAX		50

#define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0140 : 0x0100)

#define GPIO_OUT(pin)		(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)

#define GPIO_IO_CONF(pin)	(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)

#define GPIO_BLINK_EN(pin)	(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)

#define GPIO_IN_POL(pin)	(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)

#define GPIO_DATA_IN(pin)	(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)

#define GPIO_EDGE_CAUSE(pin)	(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)

#define GPIO_EDGE_MASK(pin)	(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)

#define GPIO_LEVEL_MASK(pin)	(DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)



static inline int gpio_to_irq(int pin)

{

	return pin + IRQ_KIRKWOOD_GPIO_START;

}



static inline int irq_to_gpio(int irq)

{

	return irq - IRQ_KIRKWOOD_GPIO_START;

}





#endif

arch/arm/mach-kirkwood/include/mach/kirkwood.h

+2 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ 
#define DEV_BUS_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x10000)

#define  SAMPLE_AT_RESET	(DEV_BUS_VIRT_BASE | 0x0030)

#define  DEVICE_ID		(DEV_BUS_VIRT_BASE | 0x0034)

#define  GPIO_LOW_VIRT_BASE	(DEV_BUS_VIRT_BASE | 0x0100)

#define  GPIO_HIGH_VIRT_BASE	(DEV_BUS_VIRT_BASE | 0x0140)

#define  RTC_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x0300)

#define  SPI_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x0600)

#define  I2C_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x1000)

CRA Git | Maintained and supported by SUSTech CRA and CCSE