Commit 9ea67d14 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-5.4' of... 

Merge tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX clock changes from Shawn Guo:

 - Add clock driver for i.MX8MN SoC
 - Switch i.MX8MM clock driver to platform driver
 - Add API for clk unregister when driver probe fail
 - Add Hifi4 DSP related clocks for i.MX8QXP SoC
 - Fix Audio PLL setting and parent clock for USB
 - Misc i.MX8 clock driver improvements and corrections

* tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (28 commits)
  clk: imx: imx8mn: fix audio pll setting
  clk: imx8mn: Add necessary frequency support for ARM PLL table
  clk: imx8mn: Add missing rate_count assignment for each PLL structure
  clk: imx8mn: fix int pll clk gate
  clk: imx8mn: Add GIC clock
  clk: imx8mn: Fix incorrect parents
  clk: imx8mm: Fix incorrect parents
  clk: imx8mq: Fix sys3 pll references
  clk: imx8mq: Unregister clks when of_clk_add_provider failed
  clk: imx8mm: Unregister clks when of_clk_add_provider failed
  clk: imx8mq: Mark AHB clock as critical
  clk: imx8mn: Keep uart clocks on for early console
  clk: imx: Remove unused function statement
  clk: imx7ulp: Make sure earlycon's clock is enabled
  clk: imx8mm: Switch to platform driver
  clk: imx: imx8mm: fix audio pll setting
  clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m
  clk: imx8mm: Fix typo of pwm3 clock's mux option #4
  clk: imx: Remove unused clk based API
  clk: imx8mq: set correct parent for usb ctrl clocks
  ...
parents 5f9e832c 760e548e

Documentation/devicetree/bindings/clock/imx8mn-clock.yaml

0 → 100644
+112 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8M Nano Clock Control Module Binding



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description: |

  NXP i.MX8M Nano clock control module is an integrated clock controller, which

  generates and supplies to all modules.



properties:

  compatible:

    const: fsl,imx8mn-ccm



  reg:

    maxItems: 1



  clocks:

    items:

      - description: 32k osc

      - description: 24m osc

      - description: ext1 clock input

      - description: ext2 clock input

      - description: ext3 clock input

      - description: ext4 clock input



  clock-names:

    items:

      - const: osc_32k

      - const: osc_24m

      - const: clk_ext1

      - const: clk_ext2

      - const: clk_ext3

      - const: clk_ext4



  '#clock-cells':

    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h

      for the full list of i.MX8M Nano clock IDs.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



examples:

  # Clock Control Module node:

  - |

    clk: clock-controller@30380000 {

        compatible = "fsl,imx8mn-ccm";

        reg = <0x0 0x30380000 0x0 0x10000>;

        #clock-cells = <1>;

        clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,

                 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;

        clock-names = "osc_32k", "osc_24m", "clk_ext1",

                      "clk_ext2", "clk_ext3", "clk_ext4";

    };



  # Required external clocks for Clock Control Module node:

  - |

    osc_32k: clock-osc-32k {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <32768>;

        clock-output-names = "osc_32k";

    };



    osc_24m: clock-osc-24m {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <24000000>;

        clock-output-names = "osc_24m";

    };



    clk_ext1: clock-ext1 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <133000000>;

        clock-output-names = "clk_ext1";

    };



    clk_ext2: clock-ext2 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <133000000>;

        clock-output-names = "clk_ext2";

    };



    clk_ext3: clock-ext3 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <133000000>;

        clock-output-names = "clk_ext3";

    };



    clk_ext4: clock-ext4 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency= <133000000>;

        clock-output-names = "clk_ext4";

    };



...

drivers/clk/imx/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -14,6 +14,12 @@ config CLK_IMX8MM 
	help

	    Build the driver for i.MX8MM CCM Clock Driver



config CLK_IMX8MN

	bool "IMX8MN CCM Clock Driver"

	depends on ARCH_MXC && ARM64

	help

	    Build the driver for i.MX8MN CCM Clock Driver



config CLK_IMX8MQ

	bool "IMX8MQ CCM Clock Driver"

	depends on ARCH_MXC && ARM64

drivers/clk/imx/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \ 
	clk-lpcg-scu.o



obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o

obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o

obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o

obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o

drivers/clk/imx/clk-imx7ulp.c

+31 −0
Original line number Diff line number Diff line
@@ -42,6 +42,19 @@ static const struct clk_div_table ulp_div_table[] = { 
	{ .val = 7, .div = 64, },

};



static const int pcc2_uart_clk_ids[] __initconst = {

	IMX7ULP_CLK_LPUART4,

	IMX7ULP_CLK_LPUART5,

};



static const int pcc3_uart_clk_ids[] __initconst = {

	IMX7ULP_CLK_LPUART6,

	IMX7ULP_CLK_LPUART7,

};



static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;

static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;



static void __init imx7ulp_clk_scg1_init(struct device_node *np)

{

	struct clk_hw_onecell_data *clk_data;
@@ -135,6 +148,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np) 
	struct clk_hw_onecell_data *clk_data;

	struct clk_hw **clks;

	void __iomem *base;

	int i;



	clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),

			   GFP_KERNEL);
@@ -173,6 +187,14 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np) 
	imx_check_clk_hws(clks, clk_data->num);



	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);



	for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {

		int index = pcc2_uart_clk_ids[i];



		pcc2_uart_clks[i] = &clks[index]->clk;

	}



	imx_register_uart_clocks(pcc2_uart_clks);

}

CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
@@ -181,6 +203,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np) 
	struct clk_hw_onecell_data *clk_data;

	struct clk_hw **clks;

	void __iomem *base;

	int i;



	clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),

			   GFP_KERNEL);
@@ -218,6 +241,14 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np) 
	imx_check_clk_hws(clks, clk_data->num);



	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);



	for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {

		int index = pcc3_uart_clk_ids[i];



		pcc3_uart_clks[i] = &clks[index]->clk;

	}



	imx_register_uart_clocks(pcc3_uart_clks);

}

CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);

drivers/clk/imx/clk-imx8mm.c

+56 −53
Original line number Diff line number Diff line
@@ -22,27 +22,10 @@ static u32 share_count_sai3; 
static u32 share_count_sai4;

static u32 share_count_sai5;

static u32 share_count_sai6;

static u32 share_count_dcss;

static u32 share_count_disp;

static u32 share_count_pdm;

static u32 share_count_nand;



#define PLL_1416X_RATE(_rate, _m, _p, _s)		\

	{						\

		.rate	=	(_rate),		\

		.mdiv	=	(_m),			\

		.pdiv	=	(_p),			\

		.sdiv	=	(_s),			\

	}



#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)		\

	{						\

		.rate	=	(_rate),		\

		.mdiv	=	(_m),			\

		.pdiv	=	(_p),			\

		.sdiv	=	(_s),			\

		.kdiv	=	(_k),			\

	}



static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {

	PLL_1416X_RATE(1800000000U, 225, 3, 0),

	PLL_1416X_RATE(1600000000U, 200, 3, 0),
@@ -55,8 +38,8 @@ static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = { 
};



static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = {

	PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),

	PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),

	PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),

	PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),

};



static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = {
@@ -68,43 +51,43 @@ static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = { 
	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),

};



static struct imx_pll14xx_clk imx8mm_audio_pll __initdata = {

static struct imx_pll14xx_clk imx8mm_audio_pll = {

		.type = PLL_1443X,

		.rate_table = imx8mm_audiopll_tbl,

		.rate_count = ARRAY_SIZE(imx8mm_audiopll_tbl),

};



static struct imx_pll14xx_clk imx8mm_video_pll __initdata = {

static struct imx_pll14xx_clk imx8mm_video_pll = {

		.type = PLL_1443X,

		.rate_table = imx8mm_videopll_tbl,

		.rate_count = ARRAY_SIZE(imx8mm_videopll_tbl),

};



static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {

static struct imx_pll14xx_clk imx8mm_dram_pll = {

		.type = PLL_1443X,

		.rate_table = imx8mm_drampll_tbl,

		.rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),

};



static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {

static struct imx_pll14xx_clk imx8mm_arm_pll = {

		.type = PLL_1416X,

		.rate_table = imx8mm_pll1416x_tbl,

		.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),

};



static struct imx_pll14xx_clk imx8mm_gpu_pll __initdata = {

static struct imx_pll14xx_clk imx8mm_gpu_pll = {

		.type = PLL_1416X,

		.rate_table = imx8mm_pll1416x_tbl,

		.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),

};



static struct imx_pll14xx_clk imx8mm_vpu_pll __initdata = {

static struct imx_pll14xx_clk imx8mm_vpu_pll = {

		.type = PLL_1416X,

		.rate_table = imx8mm_pll1416x_tbl,

		.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),

};



static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {

static struct imx_pll14xx_clk imx8mm_sys_pll = {

		.type = PLL_1416X,

		.rate_table = imx8mm_pll1416x_tbl,

		.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
@@ -192,10 +175,10 @@ static const char *imx8mm_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8 
static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",

					   "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };



static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m",

static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",

					      "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };



static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m",

static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",

						"sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };



static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
@@ -249,7 +232,7 @@ static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll 
static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m",

					 "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", };



static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",

static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",

					 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };



static const char *imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
@@ -304,13 +287,13 @@ static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1 
					 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };



static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",

					 "sys3_pll2_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };

					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };



static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",

					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };



static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",

					 "video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" };

					 "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };



static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",

					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
@@ -364,7 +347,7 @@ static const char *imx8mm_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_ 
					"sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };



static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",

					   "audio_pll2_out", "sys_pll2_125m", "sys_pll3_clk", "audio_pll1_out", };

					   "audio_pll2_out", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };



static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
@@ -374,7 +357,7 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", 
static struct clk *clks[IMX8MM_CLK_END];

static struct clk_onecell_data clk_data;



static struct clk ** const uart_clks[] __initconst = {

static struct clk ** const uart_clks[] = {

	&clks[IMX8MM_CLK_UART1_ROOT],

	&clks[IMX8MM_CLK_UART2_ROOT],

	&clks[IMX8MM_CLK_UART3_ROOT],
@@ -382,19 +365,20 @@ static struct clk ** const uart_clks[] __initconst = { 
	NULL

};



static int __init imx8mm_clocks_init(struct device_node *ccm_node)

static int imx8mm_clocks_probe(struct platform_device *pdev)

{

	struct device_node *np;

	struct device *dev = &pdev->dev;

	struct device_node *np = dev->of_node;

	void __iomem *base;

	int ret;



	clks[IMX8MM_CLK_DUMMY] = imx_clk_fixed("dummy", 0);

	clks[IMX8MM_CLK_24M] = of_clk_get_by_name(ccm_node, "osc_24m");

	clks[IMX8MM_CLK_32K] = of_clk_get_by_name(ccm_node, "osc_32k");

	clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");

	clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");

	clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");

	clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");

	clks[IMX8MM_CLK_24M] = of_clk_get_by_name(np, "osc_24m");

	clks[IMX8MM_CLK_32K] = of_clk_get_by_name(np, "osc_32k");

	clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");

	clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");

	clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");

	clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");



	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");

	base = of_iomap(np, 0);
@@ -480,10 +464,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) 
	clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);

	clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);



	np = ccm_node;

	base = of_iomap(np, 0);

	if (WARN_ON(!base))

		return -ENOMEM;

	np = dev->of_node;

	base = devm_platform_ioremap_resource(pdev, 0);

	if (WARN_ON(IS_ERR(base)))

		return PTR_ERR(base);



	/* Core Slice */

	clks[IMX8MM_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
@@ -631,7 +615,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) 
	clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);

	clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);

	clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);

	clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);

	clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);

	clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0);

	clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);

	clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
@@ -644,10 +628,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) 
	clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0);

	clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);

	clks[IMX8MM_CLK_PDM_IPG]  = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);

	clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss);

	clks[IMX8MM_CLK_DISP_AXI_ROOT]  = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);

	clks[IMX8MM_CLK_DISP_APB_ROOT]  = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);

	clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);

	clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_disp);

	clks[IMX8MM_CLK_DISP_AXI_ROOT]  = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);

	clks[IMX8MM_CLK_DISP_APB_ROOT]  = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);

	clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_disp);

	clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);

	clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);

	clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0);
@@ -675,11 +659,30 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) 
	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	if (ret < 0) {

		pr_err("failed to register clks for i.MX8MM\n");

		return -EINVAL;

		goto unregister_clks;

	}



	imx_register_uart_clocks(uart_clks);



	return 0;



unregister_clks:

	imx_unregister_clocks(clks, ARRAY_SIZE(clks));



	return ret;

}

CLK_OF_DECLARE_DRIVER(imx8mm, "fsl,imx8mm-ccm", imx8mm_clocks_init);
 


static const struct of_device_id imx8mm_clk_of_match[] = {

	{ .compatible = "fsl,imx8mm-ccm" },

	{ /* Sentinel */ },

};

MODULE_DEVICE_TABLE(of, imx8mm_clk_of_match);



static struct platform_driver imx8mm_clk_driver = {

	.probe = imx8mm_clocks_probe,

	.driver = {

		.name = "imx8mm-ccm",

		.of_match_table = of_match_ptr(imx8mm_clk_of_match),

	},

};

module_platform_driver(imx8mm_clk_driver);

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