Commit 9ea03dec authored Mar 16, 2013 by Ambresh K Committed by Greg Kroah-Hartman Mar 25, 2013

memory: emif: setup LP settings on freq update



Program the power management shadow register on freq update
Else the concept of threshold frequencies dont really matter
as the system always uses the performance mode timing for LP
which is programmed in at init time.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 0a5f19cf

drivers/memory/emif.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -819,6 +819,8 @@ static void setup_registers(struct emif_data emif, struct emif_regs regs)

		writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
		writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
		writel(regs->pwr_mgmt_ctrl_shdw,
		base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);

		/* Settings specific for EMIF4D5 */
		if (emif->plat_data->ip_rev != EMIF_4D5)

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