drm/i915: Add function to set subslices (9e8a135e) · Commits · 戴 / test

drivers/gpu/drm/i915/gt/intel_sseu.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -32,6 +32,12 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
		return total;
		}

		void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
		u8 ss_mask)
		{
		sseu->subslice_mask[slice] = ss_mask;
		}

		unsigned int
		intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
		{

drivers/gpu/drm/i915/gt/intel_sseu.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -78,6 +78,9 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
		unsigned int
		intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);

		void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
		u8 ss_mask);

		u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
		const struct intel_sseu *req_sseu);

drivers/gpu/drm/i915/intel_device_info.c

+11 −7

Original line number	Diff line number	Diff line
		@@ -206,7 +206,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
		int ss;

		sseu->slice_mask \|= BIT(s);
		sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;

		intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
		ss_en_mask);

		for (ss = 0; ss < sseu->max_subslices; ss++) {
		if (sseu->subslice_mask[s] & BIT(ss))
		sseu_set_eus(sseu, s, ss, eu_en);
		@@ -274,8 +277,9 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
		* Slice0 can have up to 3 subslices, but there are only 2 in
		* slice1/2.
		*/
		sseu->subslice_mask[s] = s == 0 ? subslice_mask_with_eus :
		subslice_mask_with_eus & 0x3;
		intel_sseu_set_subslices(sseu, s, s == 0 ?
		subslice_mask_with_eus :
		subslice_mask_with_eus & 0x3);
		}

		sseu->eu_total = compute_eu_total(sseu);
		@@ -330,7 +334,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
		}

		sseu->subslice_mask[0] = subslice_mask;
		intel_sseu_set_subslices(sseu, 0, subslice_mask);

		sseu->eu_total = compute_eu_total(sseu);

		@@ -384,7 +388,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
		/* skip disabled slice */
		continue;

		sseu->subslice_mask[s] = subslice_mask;
		intel_sseu_set_subslices(sseu, s, subslice_mask);

		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
		for (ss = 0; ss < sseu->max_subslices; ss++) {
		@@ -491,7 +495,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
		/* skip disabled slice */
		continue;

		sseu->subslice_mask[s] = subslice_mask;
		intel_sseu_set_subslices(sseu, s, subslice_mask);

		for (ss = 0; ss < sseu->max_subslices; ss++) {
		u8 eu_disabled_mask;
		@@ -588,7 +592,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
		sseu->eu_per_subslice);

		for (s = 0; s < sseu->max_slices; s++) {
		sseu->subslice_mask[s] = subslice_mask;
		intel_sseu_set_subslices(sseu, s, subslice_mask);

		for (ss = 0; ss < sseu->max_subslices; ss++) {
		sseu_set_eus(sseu, s, ss,

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