Commit 9e773aee authored by Rob Herring's avatar Rob Herring Committed by Will Deacon
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iommu/arm-smmu-v3: Batch ATC invalidation commands 



Similar to commit 2af2e72b ("iommu/arm-smmu-v3: Defer TLB
invalidation until ->iotlb_sync()"), build up a list of ATC invalidation
commands and submit them all at once to the command queue instead of
one-by-one.

As there is only one caller of arm_smmu_atc_inv_master() left, we can
simplify it and avoid passing in struct arm_smmu_cmdq_ent.

Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>
Cc: Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Joerg Roedel <joro@8bytes.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent edd0351e

drivers/iommu/arm-smmu-v3.c

+18 −13
Original line number Diff line number Diff line
@@ -2158,17 +2158,16 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size, 
	cmd->atc.size	= log2_span;

}



static int arm_smmu_atc_inv_master(struct arm_smmu_master *master,

				   struct arm_smmu_cmdq_ent *cmd)

static int arm_smmu_atc_inv_master(struct arm_smmu_master *master)

{

	int i;

	struct arm_smmu_cmdq_ent cmd;



	if (!master->ats_enabled)

		return 0;

	arm_smmu_atc_inv_to_cmd(0, 0, 0, &cmd);



	for (i = 0; i < master->num_sids; i++) {

		cmd->atc.sid = master->sids[i];

		arm_smmu_cmdq_issue_cmd(master->smmu, cmd);

		cmd.atc.sid = master->sids[i];

		arm_smmu_cmdq_issue_cmd(master->smmu, &cmd);

	}



	return arm_smmu_cmdq_issue_sync(master->smmu);
@@ -2177,10 +2176,11 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_master *master, 
static int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain,

				   int ssid, unsigned long iova, size_t size)

{

	int ret = 0;

	int i;

	unsigned long flags;

	struct arm_smmu_cmdq_ent cmd;

	struct arm_smmu_master *master;

	struct arm_smmu_cmdq_batch cmds = {};



	if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS))

		return 0;
@@ -2205,11 +2205,18 @@ static int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, 
	arm_smmu_atc_inv_to_cmd(ssid, iova, size, &cmd);



	spin_lock_irqsave(&smmu_domain->devices_lock, flags);

	list_for_each_entry(master, &smmu_domain->devices, domain_head)

		ret |= arm_smmu_atc_inv_master(master, &cmd);

	list_for_each_entry(master, &smmu_domain->devices, domain_head) {

		if (!master->ats_enabled)

			continue;



		for (i = 0; i < master->num_sids; i++) {

			cmd.atc.sid = master->sids[i];

			arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd);

		}

	}

	spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);



	return ret ? -ETIMEDOUT : 0;

	return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds);

}



/* IO_PGTABLE API */
@@ -2629,7 +2636,6 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master) 


static void arm_smmu_disable_ats(struct arm_smmu_master *master)

{

	struct arm_smmu_cmdq_ent cmd;

	struct arm_smmu_domain *smmu_domain = master->domain;



	if (!master->ats_enabled)
@@ -2641,8 +2647,7 @@ static void arm_smmu_disable_ats(struct arm_smmu_master *master) 
	 * ATC invalidation via the SMMU.

	 */

	wmb();

	arm_smmu_atc_inv_to_cmd(0, 0, 0, &cmd);

	arm_smmu_atc_inv_master(master, &cmd);

	arm_smmu_atc_inv_master(master);

	atomic_dec(&smmu_domain->nr_ats_masters);

}

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