EDAC, mpc85xx: Drop setting/clearing RFXE bit in HID1 (9e6a03a0) · Commits · 戴 / test

On e500v1, read fault exception enable (RFXE) controls whether assertion of core_fault_in causes a machine check interrupt. Assertion of core_fault_in can result from uncorrectable data error, such as an L2 multi-bit ECC error. It can also occur from a system error if logic on the integrated device signals a fault for nonfatal errors. RFXE bit is cleared out of reset, and should be left clear for normal operation. Assertion of core_fault_in does not cause a machine check. RFXE is set specifically for RIO (Rapid IO) and PCI for book E to catch the errors by machine check. With this bit set, the EDAC driver can't get the interrupt in case of uncorrectable error. So this bit is cleared in favor of EDAC. However, the benefit of catching such uncorrectable error doesn't outweigh the other errors which may hang the system. Besides, e500v2 has different errors masked by RFXE, and e500mc doesn't support this bit. It is more reasonable to leave RFXE as is in the EDAC driver, and leave the uncorrectable errors triggering machine check for e500v1. Suggested-by:

Scott Wood <oss@buserror.net> Signed-off-by:

York Sun <york.sun@nxp.com> Cc: Johannes Thumshirn <morbidrsa@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: oss@buserror.net Cc: stuart.yoder@nxp.com Link: http://lkml.kernel.org/r/1470779760-16483-2-git-send-email-york.sun@nxp.com Signed-off-by:

Borislav Petkov <bp@suse.de>

drivers/edac/mpc85xx_edac.c

+0 −40

Original line number	Diff line number	Diff line
		@@ -46,9 +46,6 @@ static u32 orig_pci_err_en;
		#endif

		static u32 orig_l2_err_disable;
		#ifdef CONFIG_FSL_SOC_BOOKE
		static u32 orig_hid1[2];
		#endif

		/********************** MC SYSFS parts *********************************/

		@@ -1231,14 +1228,6 @@ static struct platform_driver mpc85xx_mc_err_driver = {
		},
		};

		#ifdef CONFIG_FSL_SOC_BOOKE
		static void __init mpc85xx_mc_clear_rfxe(void *data)
		{
		orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
		mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
		}
		#endif

		static struct platform_driver * const drivers[] = {
		&mpc85xx_mc_err_driver,
		&mpc85xx_l2_err_driver,
		@@ -1269,42 +1258,13 @@ static int __init mpc85xx_mc_init(void)
		if (res)
		printk(KERN_WARNING EDAC_MOD_STR "drivers fail to register\n");

		#ifdef CONFIG_FSL_SOC_BOOKE
		pvr = mfspr(SPRN_PVR);

		if ((PVR_VER(pvr) == PVR_VER_E500V1) \|\|
		(PVR_VER(pvr) == PVR_VER_E500V2)) {
		/*
		* need to clear HID1[RFXE] to disable machine check int
		* so we can catch it
		*/
		if (edac_op_state == EDAC_OPSTATE_INT)
		on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
		}
		#endif

		return 0;
		}

		module_init(mpc85xx_mc_init);

		#ifdef CONFIG_FSL_SOC_BOOKE
		static void __exit mpc85xx_mc_restore_hid1(void *data)
		{
		mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
		}
		#endif

		static void __exit mpc85xx_mc_exit(void)
		{
		#ifdef CONFIG_FSL_SOC_BOOKE
		u32 pvr = mfspr(SPRN_PVR);

		if ((PVR_VER(pvr) == PVR_VER_E500V1) \|\|
		(PVR_VER(pvr) == PVR_VER_E500V2)) {
		on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
		}
		#endif
		platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
		}

Admin message