Commit 9e6337e6 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8m: assign clocks for A53 



Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and
assign IMX8M*_CLK_A53_CORE's parent to arm pll out as what
is done in drivers/clk/imx/clk-imx8m*.c, then we could remove
the settings in driver which triggers lockdep warning.

Reported-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent a0a44420

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+7 −3
Original line number Diff line number Diff line
@@ -519,16 +519,20 @@ 
					 <&clk_ext3>, <&clk_ext4>;

				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",

					      "clk_ext3", "clk_ext4";

				assigned-clocks = <&clk IMX8MM_CLK_NOC>,

				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,

						<&clk IMX8MM_CLK_A53_CORE>,

						<&clk IMX8MM_CLK_NOC>,

						<&clk IMX8MM_CLK_AUDIO_AHB>,

						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,

						<&clk IMX8MM_SYS_PLL3>,

						<&clk IMX8MM_VIDEO_PLL1>,

						<&clk IMX8MM_AUDIO_PLL1>,

						<&clk IMX8MM_AUDIO_PLL2>;

				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,

				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,

							 <&clk IMX8MM_ARM_PLL_OUT>,

							 <&clk IMX8MM_SYS_PLL3_OUT>,

							 <&clk IMX8MM_SYS_PLL1_800M>;

				assigned-clock-rates = <0>,

				assigned-clock-rates = <0>, <0>, <0>,

							<400000000>,

							<400000000>,

							<750000000>,

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+7 −3
Original line number Diff line number Diff line
@@ -426,13 +426,17 @@ 
					 <&clk_ext3>, <&clk_ext4>;

				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",

					      "clk_ext3", "clk_ext4";

				assigned-clocks = <&clk IMX8MN_CLK_NOC>,

				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,

						<&clk IMX8MN_CLK_A53_CORE>,

						<&clk IMX8MN_CLK_NOC>,

						<&clk IMX8MN_CLK_AUDIO_AHB>,

						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,

						<&clk IMX8MN_SYS_PLL3>;

				assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,

				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,

							 <&clk IMX8MN_ARM_PLL_OUT>,

							 <&clk IMX8MN_SYS_PLL3_OUT>,

							 <&clk IMX8MN_SYS_PLL1_800M>;

				assigned-clock-rates = <0>,

				assigned-clock-rates = <0>, <0>, <0>,

							<400000000>,

							<400000000>,

							<600000000>;

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+8 −3
Original line number Diff line number Diff line
@@ -360,7 +360,9 @@ 
					 <&clk_ext3>, <&clk_ext4>;

				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",

					      "clk_ext3", "clk_ext4";

				assigned-clocks = <&clk IMX8MP_CLK_NOC>,

				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,

						  <&clk IMX8MP_CLK_A53_CORE>,

						  <&clk IMX8MP_CLK_NOC>,

						  <&clk IMX8MP_CLK_NOC_IO>,

						  <&clk IMX8MP_CLK_GIC>,

						  <&clk IMX8MP_CLK_AUDIO_AHB>,
@@ -368,12 +370,15 @@ 
						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,

						  <&clk IMX8MP_AUDIO_PLL1>,

						  <&clk IMX8MP_AUDIO_PLL2>;

				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,

				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,

							 <&clk IMX8MP_ARM_PLL_OUT>,

							 <&clk IMX8MP_SYS_PLL2_1000M>,

							 <&clk IMX8MP_SYS_PLL1_800M>,

							 <&clk IMX8MP_SYS_PLL2_500M>,

							 <&clk IMX8MP_SYS_PLL1_800M>,

							 <&clk IMX8MP_SYS_PLL1_800M>;

				assigned-clock-rates = <1000000000>,

				assigned-clock-rates = <0>, <0>,

						       <1000000000>,

						       <800000000>,

						       <500000000>,

						       <400000000>,

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+7 −2
Original line number Diff line number Diff line
@@ -595,8 +595,13 @@ 
				clock-names = "ckil", "osc_25m", "osc_27m",

				              "clk_ext1", "clk_ext2",

				              "clk_ext3", "clk_ext4";

				assigned-clocks = <&clk IMX8MQ_CLK_NOC>;

				assigned-clock-rates = <800000000>;

				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,

						  <&clk IMX8MQ_CLK_A53_CORE>,

						  <&clk IMX8MQ_CLK_NOC>;

				assigned-clock-rates = <0>, <0>,

						       <800000000>;

				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,

							 <&clk IMX8MQ_ARM_PLL_OUT>;

			};



			src: reset-controller@30390000 {

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