Commit 9e5e19f5 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-fixes-5.7-1' of... 

Merge tag 'kvmarm-fixes-5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master

KVM/arm fixes for Linux 5.7, take #1

- Prevent the userspace API from interacting directly with the HW
  stage of the virtual GIC
- Fix a couple of vGIC memory leaks
- Tighten the rules around the use of the 32bit PSCI functions
  for 64bit guest, as well as the opposite situation (matches the
  specification)
parents dee919d1 446c0768

virt/kvm/arm/psci.c

+40 −0
Original line number Diff line number Diff line
@@ -186,6 +186,33 @@ static void kvm_psci_system_reset(struct kvm_vcpu *vcpu) 
	kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_RESET);

}



static void kvm_psci_narrow_to_32bit(struct kvm_vcpu *vcpu)

{

	int i;



	/*

	 * Zero the input registers' upper 32 bits. They will be fully

	 * zeroed on exit, so we're fine changing them in place.

	 */

	for (i = 1; i < 4; i++)

		vcpu_set_reg(vcpu, i, lower_32_bits(vcpu_get_reg(vcpu, i)));

}



static unsigned long kvm_psci_check_allowed_function(struct kvm_vcpu *vcpu, u32 fn)

{

	switch(fn) {

	case PSCI_0_2_FN64_CPU_SUSPEND:

	case PSCI_0_2_FN64_CPU_ON:

	case PSCI_0_2_FN64_AFFINITY_INFO:

		/* Disallow these functions for 32bit guests */

		if (vcpu_mode_is_32bit(vcpu))

			return PSCI_RET_NOT_SUPPORTED;

		break;

	}



	return 0;

}



static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu)

{

	struct kvm *kvm = vcpu->kvm;
@@ -193,6 +220,10 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) 
	unsigned long val;

	int ret = 1;



	val = kvm_psci_check_allowed_function(vcpu, psci_fn);

	if (val)

		goto out;



	switch (psci_fn) {

	case PSCI_0_2_FN_PSCI_VERSION:

		/*
@@ -210,12 +241,16 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) 
		val = PSCI_RET_SUCCESS;

		break;

	case PSCI_0_2_FN_CPU_ON:

		kvm_psci_narrow_to_32bit(vcpu);

		fallthrough;

	case PSCI_0_2_FN64_CPU_ON:

		mutex_lock(&kvm->lock);

		val = kvm_psci_vcpu_on(vcpu);

		mutex_unlock(&kvm->lock);

		break;

	case PSCI_0_2_FN_AFFINITY_INFO:

		kvm_psci_narrow_to_32bit(vcpu);

		fallthrough;

	case PSCI_0_2_FN64_AFFINITY_INFO:

		val = kvm_psci_vcpu_affinity_info(vcpu);

		break;
@@ -256,6 +291,7 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) 
		break;

	}



out:

	smccc_set_retval(vcpu, val, 0, 0, 0);

	return ret;

}
@@ -273,6 +309,10 @@ static int kvm_psci_1_0_call(struct kvm_vcpu *vcpu) 
		break;

	case PSCI_1_0_FN_PSCI_FEATURES:

		feature = smccc_get_arg1(vcpu);

		val = kvm_psci_check_allowed_function(vcpu, feature);

		if (val)

			break;



		switch(feature) {

		case PSCI_0_2_FN_PSCI_VERSION:

		case PSCI_0_2_FN_CPU_SUSPEND:

virt/kvm/arm/vgic/vgic-init.c

+8 −2
Original line number Diff line number Diff line
@@ -348,6 +348,12 @@ void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) 
{

	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;



	/*

	 * Retire all pending LPIs on this vcpu anyway as we're

	 * going to destroy it.

	 */

	vgic_flush_pending_lpis(vcpu);



	INIT_LIST_HEAD(&vgic_cpu->ap_list_head);

}
@@ -359,10 +365,10 @@ static void __kvm_vgic_destroy(struct kvm *kvm) 


	vgic_debug_destroy(kvm);



	kvm_vgic_dist_destroy(kvm);



	kvm_for_each_vcpu(i, vcpu, kvm)

		kvm_vgic_vcpu_destroy(vcpu);



	kvm_vgic_dist_destroy(kvm);

}



void kvm_vgic_destroy(struct kvm *kvm)

virt/kvm/arm/vgic/vgic-its.c

+9 −2
Original line number Diff line number Diff line
@@ -96,14 +96,21 @@ out_unlock: 
	 * We "cache" the configuration table entries in our struct vgic_irq's.

	 * However we only have those structs for mapped IRQs, so we read in

	 * the respective config data from memory here upon mapping the LPI.

	 *

	 * Should any of these fail, behave as if we couldn't create the LPI

	 * by dropping the refcount and returning the error.

	 */

	ret = update_lpi_config(kvm, irq, NULL, false);

	if (ret)

	if (ret) {

		vgic_put_irq(kvm, irq);

		return ERR_PTR(ret);

	}



	ret = vgic_v3_lpi_sync_pending_status(kvm, irq);

	if (ret)

	if (ret) {

		vgic_put_irq(kvm, irq);

		return ERR_PTR(ret);

	}



	return irq;

}

virt/kvm/arm/vgic/vgic-mmio-v2.c

+10 −6
Original line number Diff line number Diff line
@@ -409,24 +409,28 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { 
		NULL, vgic_mmio_uaccess_write_v2_group, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,

		vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,

		vgic_mmio_read_enable, vgic_mmio_write_senable,

		NULL, vgic_uaccess_write_senable, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,

		vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,

		vgic_mmio_read_enable, vgic_mmio_write_cenable,

		NULL, vgic_uaccess_write_cenable, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,

		vgic_mmio_read_pending, vgic_mmio_write_spending, NULL, NULL, 1,

		vgic_mmio_read_pending, vgic_mmio_write_spending,

		NULL, vgic_uaccess_write_spending, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,

		vgic_mmio_read_pending, vgic_mmio_write_cpending, NULL, NULL, 1,

		vgic_mmio_read_pending, vgic_mmio_write_cpending,

		NULL, vgic_uaccess_write_cpending, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,

		vgic_mmio_read_active, vgic_mmio_write_sactive,

		NULL, vgic_mmio_uaccess_write_sactive, 1,

		vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,

		vgic_mmio_read_active, vgic_mmio_write_cactive,

		NULL, vgic_mmio_uaccess_write_cactive, 1,

		vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,

		vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,

virt/kvm/arm/vgic/vgic-mmio-v3.c

+16 −12
Original line number Diff line number Diff line
@@ -538,10 +538,12 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = { 
		vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,

		vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,

		vgic_mmio_read_enable, vgic_mmio_write_senable,

		NULL, vgic_uaccess_write_senable, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,

		vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,

		vgic_mmio_read_enable, vgic_mmio_write_cenable,

	       NULL, vgic_uaccess_write_cenable, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,

		vgic_mmio_read_pending, vgic_mmio_write_spending,
@@ -553,11 +555,11 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = { 
		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,

		vgic_mmio_read_active, vgic_mmio_write_sactive,

		NULL, vgic_mmio_uaccess_write_sactive, 1,

		vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,

		vgic_mmio_read_active, vgic_mmio_write_cactive,

		NULL, vgic_mmio_uaccess_write_cactive,

		vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive,

		1, VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,

		vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
@@ -609,11 +611,13 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = { 
	REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,

		vgic_mmio_read_group, vgic_mmio_write_group, 4,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISENABLER0,

		vgic_mmio_read_enable, vgic_mmio_write_senable, 4,

	REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0,

		vgic_mmio_read_enable, vgic_mmio_write_senable,

		NULL, vgic_uaccess_write_senable, 4,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICENABLER0,

		vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,

	REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0,

		vgic_mmio_read_enable, vgic_mmio_write_cenable,

		NULL, vgic_uaccess_write_cenable, 4,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,

		vgic_mmio_read_pending, vgic_mmio_write_spending,
@@ -625,12 +629,12 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = { 
		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0,

		vgic_mmio_read_active, vgic_mmio_write_sactive,

		NULL, vgic_mmio_uaccess_write_sactive,

		4, VGIC_ACCESS_32bit),

		vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0,

		vgic_mmio_read_active, vgic_mmio_write_cactive,

		NULL, vgic_mmio_uaccess_write_cactive,

		4, VGIC_ACCESS_32bit),

		vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4,

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,

		vgic_mmio_read_priority, vgic_mmio_write_priority, 32,

		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),

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