Commit 9e586c84 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux into arm/drivers 

Reset controller updates for v5.9

This tag moves the reset-simple header out of drivers/reset for use by
drivers outside of drivers/reset, adds a .reset() callback to
reset-simple, converts i.MX reset bindings to json-schema, fixes a
compile warning in the reset-intel-gw driver, and replaces some HTTP
links with HTTPS ones in comments.

* tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux:
  reset: Replace HTTP links with HTTPS ones
  reset: intel: fix a compile warning about REG_OFFSET redefined
  dt-bindings: reset: Convert i.MX7 reset to json-schema
  dt-bindings: reset: Convert i.MX reset to json-schema
  reset: simple: Add reset callback
  reset: Move reset-simple header out of drivers/reset

Link: https://lore.kernel.org/r/b718f052e38abbaac599d80645376b75e54aa5bd.camel@pengutronix.de


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 00067ca5 ffebbeca

Documentation/devicetree/bindings/reset/fsl,imx-src.txt

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Freescale i.MX System Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "fsl,<chip>-src"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,

  in this order.

- #reset-cells: 1, see below



example:



src: src@20d8000 {

        compatible = "fsl,imx6q-src";

        reg = <0x020d8000 0x4000>;

        interrupts = <0 91 0x04 0 96 0x04>;

        #reset-cells = <1>;

};



Specifying reset lines connected to IP modules

==============================================



The system reset controller can be used to reset the GPU, VPU,

IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device

nodes should specify the reset line on the SRC in their resets

property, containing a phandle to the SRC device node and a

RESET_INDEX specifying which module to reset, as described in

reset.txt



example:



        ipu1: ipu@2400000 {

                resets = <&src 2>;

        };

        ipu2: ipu@2800000 {

                resets = <&src 4>;

        };



The following RESET_INDEX values are valid for i.MX5:

GPU_RESET     0

VPU_RESET     1

IPU1_RESET    2

OPEN_VG_RESET 3

The following additional RESET_INDEX value is valid for i.MX6:

IPU2_RESET    4

Documentation/devicetree/bindings/reset/fsl,imx-src.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX System Reset Controller



maintainers:

  - Philipp Zabel <p.zabel@pengutronix.de>



description: |

  The system reset controller can be used to reset the GPU, VPU,

  IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device

  nodes should specify the reset line on the SRC in their resets

  property, containing a phandle to the SRC device node and a

  RESET_INDEX specifying which module to reset, as described in

  reset.txt



  The following RESET_INDEX values are valid for i.MX5:

    GPU_RESET     0

    VPU_RESET     1

    IPU1_RESET    2

    OPEN_VG_RESET 3

  The following additional RESET_INDEX value is valid for i.MX6:

    IPU2_RESET    4



properties:

  compatible:

    oneOf:

      - const: "fsl,imx51-src"

      - items:

          - const: "fsl,imx50-src"

          - const: "fsl,imx51-src"

      - items:

          - const: "fsl,imx53-src"

          - const: "fsl,imx51-src"

      - items:

          - const: "fsl,imx6q-src"

          - const: "fsl,imx51-src"

      - items:

          - const: "fsl,imx6sx-src"

          - const: "fsl,imx51-src"

      - items:

          - const: "fsl,imx6sl-src"

          - const: "fsl,imx51-src"

      - items:

          - const: "fsl,imx6ul-src"

          - const: "fsl,imx51-src"

      - items:

          - const: "fsl,imx6sll-src"

          - const: "fsl,imx51-src"



  reg:

    maxItems: 1



  interrupts:

    items:

      - description: SRC interrupt

      - description: CPU WDOG interrupts out of SRC

    minItems: 1

    maxItems: 2



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - interrupts

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    reset-controller@73fd0000 {

        compatible = "fsl,imx51-src";

        reg = <0x73fd0000 0x4000>;

        interrupts = <75>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

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Freescale i.MX7 System Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible:

	- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"

	- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"

	- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"

	- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"

	- For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt

- #reset-cells: 1, see below



example:



src: reset-controller@30390000 {

     compatible = "fsl,imx7d-src", "syscon";

     reg = <0x30390000 0x2000>;

     interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

     #reset-cells = <1>;

};





Specifying reset lines connected to IP modules

==============================================



The system reset controller can be used to reset various set of

peripherals. Device nodes that need access to reset lines should

specify them as a reset phandle in their corresponding node as

specified in reset.txt.



Example:



	pcie: pcie@33800000 {



		...



		resets = <&src IMX7_RESET_PCIEPHY>,

			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;

		reset-names = "pciephy", "apps";



		...

        };





For list of all valid reset indices see

<dt-bindings/reset/imx7-reset.h> for i.MX7,

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and

<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and

<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP

Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX7 System Reset Controller



maintainers:

  - Andrey Smirnov <andrew.smirnov@gmail.com>



description: |

  The system reset controller can be used to reset various set of

  peripherals. Device nodes that need access to reset lines should

  specify them as a reset phandle in their corresponding node as

  specified in reset.txt.



  For list of all valid reset indices see

    <dt-bindings/reset/imx7-reset.h> for i.MX7,

    <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,

    <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.



properties:

  compatible:

    items:

      - enum:

        - fsl,imx7d-src

        - fsl,imx8mq-src

        - fsl,imx8mp-src

      - const: syscon



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - interrupts

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    reset-controller@30390000 {

        compatible = "fsl,imx7d-src", "syscon";

        reg = <0x30390000 0x2000>;

        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

        #reset-cells = <1>;

    };

drivers/reset/reset-intel-gw.c

+12 −12
Original line number Diff line number Diff line
@@ -15,9 +15,9 @@ 
#define RCU_RST_STAT	0x0024

#define RCU_RST_REQ	0x0048



#define REG_OFFSET	GENMASK(31, 16)

#define BIT_OFFSET	GENMASK(15, 8)

#define STAT_BIT_OFFSET	GENMASK(7, 0)

#define REG_OFFSET_MASK	GENMASK(31, 16)

#define BIT_OFFSET_MASK	GENMASK(15, 8)

#define STAT_BIT_OFFSET_MASK	GENMASK(7, 0)



#define to_reset_data(x)	container_of(x, struct intel_reset_data, rcdev)
@@ -51,11 +51,11 @@ static u32 id_to_reg_and_bit_offsets(struct intel_reset_data *data, 
				     unsigned long id, u32 *rst_req,

				     u32 *req_bit, u32 *stat_bit)

{

	*rst_req = FIELD_GET(REG_OFFSET, id);

	*req_bit = FIELD_GET(BIT_OFFSET, id);

	*rst_req = FIELD_GET(REG_OFFSET_MASK, id);

	*req_bit = FIELD_GET(BIT_OFFSET_MASK, id);



	if (data->soc_data->legacy)

		*stat_bit = FIELD_GET(STAT_BIT_OFFSET, id);

		*stat_bit = FIELD_GET(STAT_BIT_OFFSET_MASK, id);

	else

		*stat_bit = *req_bit;
@@ -141,14 +141,14 @@ static int intel_reset_xlate(struct reset_controller_dev *rcdev, 
	if (spec->args[1] > 31)

		return -EINVAL;



	id = FIELD_PREP(REG_OFFSET, spec->args[0]);

	id |= FIELD_PREP(BIT_OFFSET, spec->args[1]);

	id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]);

	id |= FIELD_PREP(BIT_OFFSET_MASK, spec->args[1]);



	if (data->soc_data->legacy) {

		if (spec->args[2] > 31)

			return -EINVAL;



		id |= FIELD_PREP(STAT_BIT_OFFSET, spec->args[2]);

		id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, spec->args[2]);

	}



	return id;
@@ -210,11 +210,11 @@ static int intel_reset_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	data->reboot_id = FIELD_PREP(REG_OFFSET, rb_id[0]);

	data->reboot_id |= FIELD_PREP(BIT_OFFSET, rb_id[1]);

	data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]);

	data->reboot_id |= FIELD_PREP(BIT_OFFSET_MASK, rb_id[1]);



	if (data->soc_data->legacy)

		data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET, rb_id[2]);

		data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, rb_id[2]);



	data->restart_nb.notifier_call =	intel_reset_restart_handler;

	data->restart_nb.priority =		128;

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