Commit 9e1af756 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC updates from Ulf Hansson:
 "There are no updates for the MEMSTICK subsystem this time. But note
  that I am also carrying a patch from the pinctrl tree, which has been
  shared through an immutable branch.

  Summary:

  MMC core:
   - Convert to reasonable timeouts for all CMD6 commands (updates for
     BKOPS, CACHE_FLUSH and INAND_CMD38_ARG_EXT_CSD) for eMMC
   - Respect f_max clock rate at card initialization
   - Add gpiod_toggle_active_low() API
   - Consolidate slot-gpio code by using gpiod_toggle_active_low()

  MMC host:
   - Add pinctrl_select_default_state() API
   - Consolidate pintctrl code by using pinctrl_select_default_state()
   - mmci: Support any block sizes for SDIO for some variants
   - mmci: Enable reset control for stm32_sdmmc
   - mmc_spi: Toggle SPI_CS_HIGH polarity rather than hard-coding it
   - renesas_sdhi: Add support for the r8a77961 variant
   - renesas_sdhi: A few minor improvements
   - rockchip-dw-mshc: Add support for the rk3308 variant
   - sdhci: Enable support for external DMA controllers
   - sdhci: Fixup error path when sending CMD12
   - sdhci-brcmstb: Add support for 7216b0 variant
   - sdhci-brcmstb: Add support for command queuing (CQHCI)
   - sdhci-brcmstb: Add support for eMMC HS400ES mode
   - sdhci-msm: Add support for the sc7180 variant
   - sdhci-msm: Add support for command queuing (CQHCI)
   - sdhci-of-at91: Add support for the SAM9x60 variant
   - sdhci-of-at91: Improve support for tunings
   - sdhci-of-esdhc: A few fixups for some clock related issues
   - sdhci-omap: Add support for the am335x and the am437x variants
   - sdhci-omap: Improve support for erase operations
   - sdhci-omap: Add support for external DMA"

* tag 'mmc-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (89 commits)
  mmc: core: Default to generic_cmd6_time as timeout in __mmc_switch()
  mmc: block: Use generic_cmd6_time when modifying INAND_CMD38_ARG_EXT_CSD
  mmc: core: Specify timeouts for BKOPS and CACHE_FLUSH for eMMC
  mmc: sdhci-cadence: remove unneeded 'inline' marker
  dt-bindings: mmc: rockchip-dw-mshc: add description for rk3308
  dt-bindings: mmc: convert rockchip dw-mshc bindings to yaml
  dt-bindings: mmc: convert synopsys dw-mshc bindings to yaml
  mmc: sdhci-msm: Add CQHCI support for sdhci-msm
  mmc: sdhci: Let a vendor driver supply and update ADMA descriptor size
  mmc: sdhci-of-esdhc: fix serious issue clock is always disabled
  mmc: sdhci-of-esdhc: fix transfer mode register reading
  mmc: sdhci-brcmstb: Fix incorrect switch to HS mode
  mmc: sdhci-brcmstb: Add support for Command Queuing (CQE)
  mmc: sdhci-brcmstb: Add shutdown callback
  mmc: sdhci-brcmstb: Fix driver to defer on clk_get defer
  mmc: sdhci-brcmstb: Add ability to use HS400ES transfer mode
  dt-bindings: mmc: brcm,sdhci-brcmstb: Add support for 7216b0
  mmc: core: limit probe clock frequency to configured f_max
  mmc: sdhci-milbeaut: Remove redundant platform_get_irq error message
  mmc: sdhci: fix an issue of mixing different types
  ...
parents b9b627a4 533a6cfe

Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt

+28 −13
Original line number Diff line number Diff line
@@ -11,28 +11,43 @@ Required properties: 
- compatible: should be one of the following

  - "brcm,bcm7425-sdhci"

  - "brcm,bcm7445-sdhci"

  - "brcm,bcm7216-sdhci"



Refer to clocks/clock-bindings.txt for generic clock consumer properties.



Example:



	sdhci@f03e0100 {

		compatible = "brcm,bcm7425-sdhci";

		reg = <0xf03e0000 0x100>;

		interrupts = <0x0 0x26 0x0>;

		sdhci,auto-cmd12;

		clocks = <&sw_sdio>;

	sdhci@84b0000 {

		sd-uhs-sdr50;

		sd-uhs-ddr50;

		sd-uhs-sdr104;

		sdhci,auto-cmd12;

		compatible = "brcm,bcm7216-sdhci",

			   "brcm,bcm7445-sdhci",

			   "brcm,sdhci-brcmstb";

		reg = <0x84b0000 0x260 0x84b0300 0x200>;

		reg-names = "host", "cfg";

		interrupts = <0x0 0x26 0x4>;

		interrupt-names = "sdio0_0";

		clocks = <&scmi_clk 245>;

		clock-names = "sw_sdio";

	};



	sdhci@f03e0300 {

	sdhci@84b1000 {

		mmc-ddr-1_8v;

		mmc-hs200-1_8v;

		mmc-hs400-1_8v;

		mmc-hs400-enhanced-strobe;

		supports-cqe;

		non-removable;

		bus-width = <0x8>;

		compatible = "brcm,bcm7425-sdhci";

		reg = <0xf03e0200 0x100>;

		interrupts = <0x0 0x27 0x0>;

		sdhci,auto-cmd12;

		clocks = <sw_sdio>;

		mmc-hs200-1_8v;

		compatible = "brcm,bcm7216-sdhci",

			   "brcm,bcm7445-sdhci",

			   "brcm,sdhci-brcmstb";

		reg = <0x84b1000 0x260 0x84b1300 0x200>;

		reg-names = "host", "cfg";

		interrupts = <0x0 0x27 0x4>;

		interrupt-names = "sdio1_0";

		clocks = <&scmi_clk 245>;

		clock-names = "sw_sdio";

	};

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ Required properties: 
	       "fsl,imx8mq-usdhc"

	       "fsl,imx8mm-usdhc"

	       "fsl,imx8mn-usdhc"

	       "fsl,imx8mp-usdhc"

	       "fsl,imx8qxp-usdhc"



Optional properties:

Documentation/devicetree/bindings/mmc/renesas,sdhi.txt

+2 −1
Original line number Diff line number Diff line
@@ -23,7 +23,8 @@ Required properties: 
		"renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC

		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC

		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC

		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC

		"renesas,sdhi-r8a7796" - SDHI IP on R8A77960 SoC

		"renesas,sdhi-r8a77961" - SDHI IP on R8A77961 SoC

		"renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC

		"renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC

		"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt

deleted100644 → 0
+0 −49
Original line number Diff line number Diff line 
* Rockchip specific extensions to the Synopsys Designware Mobile

  Storage Host Controller



The Synopsys designware mobile storage host controller is used to interface

a SoC with storage medium such as eMMC or SD/MMC cards. This file documents

differences between the core Synopsys dw mshc controller properties described

by synopsys-dw-mshc.txt and the properties used by the Rockchip specific

extensions to the Synopsys Designware Mobile Storage Host Controller.



Required Properties:



* compatible: should be

	- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,

							before RK3288

	- "rockchip,rk3288-dw-mshc": for Rockchip RK3288

	- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108

	- "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip PX30

	- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036

	- "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x

	- "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328

	- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368

	- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399



Optional Properties:

* clocks: from common clock binding: if ciu-drive and ciu-sample are

  specified in clock-names, should contain handles to these clocks.



* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt

  two more clocks "ciu-drive" and "ciu-sample" are supported. They are used

  to control the clock phases, "ciu-sample" is required for tuning high-

  speed modes.



* rockchip,default-sample-phase: The default phase to set ciu-sample at

  probing, low speeds or in case where all phases work at tuning time.

  If not specified 0 deg will be used.



* rockchip,desired-num-phases: The desired number of times that the host

  execute tuning when needed. If not specified, the host will do tuning

  for 360 times, namely tuning for each degree.



Example:



	rkdwmmc0@12200000 {

		compatible = "rockchip,rk3288-dw-mshc";

		reg = <0x12200000 0x1000>;

		interrupts = <0 75 0>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml

0 → 100644
+125 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip designware mobile storage host controller device tree bindings



description:

  Rockchip uses the Synopsys designware mobile storage host controller

  to interface a SoC with storage medium such as eMMC or SD/MMC cards.

  This file documents the combined properties for the core Synopsys dw mshc

  controller that are not already included in the synopsys-dw-mshc-common.yaml

  file and the Rockchip specific extensions.



allOf:

  - $ref: "synopsys-dw-mshc-common.yaml#"



maintainers:

  - Heiko Stuebner <heiko@sntech.de>



# Everything else is described in the common file

properties:

  compatible:

    oneOf:

      # for Rockchip RK2928 and before RK3288

      - const: rockchip,rk2928-dw-mshc

      # for Rockchip RK3288

      - const: rockchip,rk3288-dw-mshc

      - items:

          - enum:

            # for Rockchip PX30

            - rockchip,px30-dw-mshc

            # for Rockchip RK3036

            - rockchip,rk3036-dw-mshc

            # for Rockchip RK322x

            - rockchip,rk3228-dw-mshc

            # for Rockchip RK3308

            - rockchip,rk3308-dw-mshc

            # for Rockchip RK3328

            - rockchip,rk3328-dw-mshc

            # for Rockchip RK3368

            - rockchip,rk3368-dw-mshc

            # for Rockchip RK3399

            - rockchip,rk3399-dw-mshc

            # for Rockchip RV1108

            - rockchip,rv1108-dw-mshc

          - const: rockchip,rk3288-dw-mshc



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    minItems: 2

    maxItems: 4

    description:

      Handle to "biu" and "ciu" clocks for the bus interface unit clock and

      the card interface unit clock. If "ciu-drive" and "ciu-sample" are

      specified in clock-names, it should also contain

      handles to these clocks.



  clock-names:

    minItems: 2

    items:

      - const: biu

      - const: ciu

      - const: ciu-drive

      - const: ciu-sample

    description:

      Apart from the clock-names "biu" and "ciu" two more clocks

      "ciu-drive" and "ciu-sample" are supported. They are used

      to control the clock phases, "ciu-sample" is required for tuning

      high speed modes.



  rockchip,default-sample-phase:

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 360

    default: 0

    description:

      The default phase to set "ciu-sample" at probing,

      low speeds or in case where all phases work at tuning time.

      If not specified 0 deg will be used.



  rockchip,desired-num-phases:

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 360

    default: 360

    description:

      The desired number of times that the host execute tuning when needed.

      If not specified, the host will do tuning for 360 times,

      namely tuning for each degree.



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



examples:

  - |

    #include <dt-bindings/clock/rk3288-cru.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    sdmmc: mmc@ff0c0000 {

      compatible = "rockchip,rk3288-dw-mshc";

      reg = <0x0 0xff0c0000 0x0 0x4000>;

      interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,

               <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;

      clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

      resets = <&cru SRST_MMC0>;

      reset-names = "reset";

      fifo-depth = <0x100>;

      max-frequency = <150000000>;

    };



...

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