Commit 9ddfd929 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
  MIPS: O32: Fix ppoll
  MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
  MIPS: Alchemy: Fix hang with high-frequency edge interrupts
  MIPS: TXx9: Fix spi-baseclk value
  MIPS: bcm63xx: Set the correct BCM3302 CPU name
  MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
  MIPS: Avoid potential hazard on Context register
  MIPS: Octeon: Use lockless interrupt controller operations when possible.
  MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
  MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
  MIPS: SMTC: Avoid queing multiple reschedule IPIs
  MIPS: GCMP: Avoid accessing registers when they are not present
  MIPS: GIC: Random fixes and enhancements.
  MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
  MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
  MIPS: SPRAM: Clean up support code a little
  MIPS: 1004K: Enable SPRAM support.
  MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
  MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
  MIPS: MTI: Fix accesses to device registers on MIPS boards
  ...
parents 38dc6345 049a31af

arch/mips/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -1012,9 +1012,9 @@ config BOOT_ELF32 


config MIPS_L1_CACHE_SHIFT

	int

	default "4" if MACH_DECSTATION || MIKROTIK_RB532

	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL

	default "6" if MIPS_CPU_SCACHE

	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON

	default "4" if PMC_MSP4200_EVAL

	default "5"



config HAVE_STD_PC_SERIAL_PORT

arch/mips/alchemy/common/irq.c

+26 −8
Original line number Diff line number Diff line
@@ -354,6 +354,28 @@ static void au1x_ic1_ack(unsigned int irq_nr) 
	au_sync();

}



static void au1x_ic0_maskack(unsigned int irq_nr)

{

	unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;



	au_writel(1 << bit, IC0_WAKECLR);

	au_writel(1 << bit, IC0_MASKCLR);

	au_writel(1 << bit, IC0_RISINGCLR);

	au_writel(1 << bit, IC0_FALLINGCLR);

	au_sync();

}



static void au1x_ic1_maskack(unsigned int irq_nr)

{

	unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;



	au_writel(1 << bit, IC1_WAKECLR);

	au_writel(1 << bit, IC1_MASKCLR);

	au_writel(1 << bit, IC1_RISINGCLR);

	au_writel(1 << bit, IC1_FALLINGCLR);

	au_sync();

}



static int au1x_ic1_setwake(unsigned int irq, unsigned int on)

{

	unsigned int bit = irq - AU1000_INTC1_INT_BASE;
@@ -379,25 +401,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 
/*

 * irq_chips for both ICs; this way the mask handlers can be

 * as short as possible.

 *

 * NOTE: the ->ack() callback is used by the handle_edge_irq

 *	 flowhandler only, the ->mask_ack() one by handle_level_irq,

 *	 so no need for an irq_chip for each type of irq (level/edge).

 */

static struct irq_chip au1x_ic0_chip = {

	.name		= "Alchemy-IC0",

	.ack		= au1x_ic0_ack,		/* edge */

	.ack		= au1x_ic0_ack,

	.mask		= au1x_ic0_mask,

	.mask_ack	= au1x_ic0_mask,	/* level */

	.mask_ack	= au1x_ic0_maskack,

	.unmask		= au1x_ic0_unmask,

	.set_type	= au1x_ic_settype,

};



static struct irq_chip au1x_ic1_chip = {

	.name		= "Alchemy-IC1",

	.ack		= au1x_ic1_ack,		/* edge */

	.ack		= au1x_ic1_ack,

	.mask		= au1x_ic1_mask,

	.mask_ack	= au1x_ic1_mask,	/* level */

	.mask_ack	= au1x_ic1_maskack,

	.unmask		= au1x_ic1_unmask,

	.set_type	= au1x_ic_settype,

	.set_wake	= au1x_ic1_setwake,

arch/mips/alchemy/mtx-1/board_setup.c

+1 −2
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ void __init board_setup(void) 
#else

	au_writel(0xf, Au1500_PCI_CFG);

#endif

	board_pci_idsel = mtx1_pci_idsel;

#endif



	/* Initialize sys_pinfunc */
@@ -85,8 +86,6 @@ void __init board_setup(void) 
	alchemy_gpio_direction_output(211, 1);	/* green on */

	alchemy_gpio_direction_output(212, 0);	/* red off */



	board_pci_idsel = mtx1_pci_idsel;



	printk(KERN_INFO "4G Systems MTX-1 Board\n");

}

arch/mips/ar7/platform.c

+8 −1
Original line number Diff line number Diff line
@@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) 
{

	u16 chip_id;

	int res;

	u32 *bootcr, val;

#ifdef CONFIG_SERIAL_8250

	static struct uart_port uart_port[2];
@@ -595,6 +596,12 @@ static int __init ar7_register_devices(void) 


	ar7_wdt_res.end = ar7_wdt_res.start + 0x20;



	bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);

	val = *bootcr;

	iounmap(bootcr);



	/* Register watchdog only if enabled in hardware */

	if (val & AR7_WDT_HW_ENA)

		res = platform_device_register(&ar7_wdt);



	return res;

arch/mips/bcm63xx/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \

		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o

		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o

obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o



obj-y		+= boards/

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