Commit 9ddebc46 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: OCTEON: Rename Kconfig CAVIUM_OCTEON_REFERENCE_BOARD to CAVIUM_OCTEON_SOC 



CAVIUM_OCTEON_SOC most place we used to use CPU_CAVIUM_OCTEON.  This
allows us to CPU_CAVIUM_OCTEON in places where we have no OCTEON SOC.

Remove CAVIUM_OCTEON_SIMULATOR as it doesn't really do anything, we can
get the same configuration with CAVIUM_OCTEON_SOC.

Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-ide@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: spi-devel-general@lists.sourceforge.net
Cc: devel@driverdev.osuosl.org
Cc: linux-usb@vger.kernel.org
Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: default avatarWolfram Sang <wsa@the-dreams.de>
Acked-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
Patchwork: https://patchwork.linux-mips.org/patch/5295/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6e7582bf

arch/mips/Kconfig

+2 −17
Original line number Diff line number Diff line
@@ -735,23 +735,8 @@ config WR_PPMC 
	  This enables support for the Wind River MIPS32 4KC PPMC evaluation

	  board, which is based on GT64120 bridge chip.



config CAVIUM_OCTEON_SIMULATOR

	bool "Cavium Networks Octeon Simulator"

	select CEVT_R4K

	select 64BIT_PHYS_ADDR

	select DMA_COHERENT

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HOTPLUG_CPU

	select SYS_HAS_CPU_CAVIUM_OCTEON

	select HOLES_IN_ZONE

	help

	  The Octeon simulator is software performance model of the Cavium

	  Octeon Processor. It supports simulating Octeon processors on x86

	  hardware.



config CAVIUM_OCTEON_REFERENCE_BOARD

	bool "Cavium Networks Octeon reference board"

config CAVIUM_OCTEON_SOC

	bool "Cavium Networks Octeon SoC based boards"

	select CEVT_R4K

	select 64BIT_PHYS_ADDR

	select DMA_COHERENT

arch/mips/cavium-octeon/Kconfig

+5 −1
Original line number Diff line number Diff line
@@ -10,6 +10,10 @@ config CAVIUM_CN63XXP1 
	  non-CN63XXP1 hardware, so it is recommended to select "n"

	  unless it is known the workarounds are needed.



endif # CPU_CAVIUM_OCTEON



if CAVIUM_OCTEON_SOC



config CAVIUM_OCTEON_2ND_KERNEL

	bool "Build the kernel to be used as a 2nd kernel on the same chip"

	default "n"
@@ -103,4 +107,4 @@ config OCTEON_ILM 
	  To compile this driver as a module, choose M here.  The module

	  will be called octeon-ilm



endif # CPU_CAVIUM_OCTEON
 
endif # CAVIUM_OCTEON_SOC

arch/mips/cavium-octeon/Platform

+4 −4
Original line number Diff line number Diff line 
#

# Cavium Octeon

#

platform-$(CONFIG_CPU_CAVIUM_OCTEON)	+= cavium-octeon/

cflags-$(CONFIG_CPU_CAVIUM_OCTEON)	+=				\

platform-$(CONFIG_CAVIUM_OCTEON_SOC)	+= cavium-octeon/

cflags-$(CONFIG_CAVIUM_OCTEON_SOC)	+=				\

		-I$(srctree)/arch/mips/include/asm/mach-cavium-octeon

ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL

load-$(CONFIG_CPU_CAVIUM_OCTEON)	+= 0xffffffff84100000

load-$(CONFIG_CAVIUM_OCTEON_SOC)	+= 0xffffffff84100000

else

load-$(CONFIG_CPU_CAVIUM_OCTEON)	+= 0xffffffff81100000

load-$(CONFIG_CAVIUM_OCTEON_SOC)	+= 0xffffffff81100000

endif

arch/mips/configs/cavium_octeon_defconfig

+1 −1
Original line number Diff line number Diff line 
CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y

CONFIG_CAVIUM_OCTEON_SOC=y

CONFIG_CAVIUM_CN63XXP1=y

CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2

CONFIG_SPARSEMEM_MANUAL=y

arch/mips/pci/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -54,10 +54,10 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 
obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capcella.o

obj-$(CONFIG_WR_PPMC)		+= fixup-wrppmc.o

obj-$(CONFIG_MIKROTIK_RB532)	+= pci-rc32434.o ops-rc32434.o fixup-rc32434.o

obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o

obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o

obj-$(CONFIG_CPU_XLR)		+= pci-xlr.o

obj-$(CONFIG_CPU_XLP)		+= pci-xlp.o



ifdef CONFIG_PCI_MSI

obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o

obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o

endif

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