Commit 9dde6da5 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
100GbE Intel Wired LAN Driver Updates 2019-01-15

This series contains updates to the ice driver only.

Bruce fixes an unused variable build warning, which was introduced with
the commit 2fd527b7 ("net: ndo_bridge_setlink: Add extack").  Added
ethtool support for get_eeprom and get_eeprom_len operations.  Added
support for bringing down the PHY link optional when the interface is
administratively downed.

Anirudh refactors the transmit scheduler functions, which results in
reduced code duplication and adds a helper function, which all the
scheduler functions call instead.  Added an LED blinking handler to
ethtool.  Reworked the queue management code to allow for reuse in
future XDP feature support.  Updates the driver to be able to preserve
the aggregator list after reset by moving it out of port_info and into
ice_hw.  Added the ability to offload SCTP checksum calculation to the
hardware.  Added support for new PHY types, which support higher link
speeds.

Md Fahad makes sure that RSS lookup table and hash key get configured
during the rebuild path after a reset.

Brett updates the driver to set the physical link state according to the
netdev state (up/down).  Added support for adaptive/dynamic interrupt
moderation in the ice driver, along with the ethtool operations needed.

Tony adds software timestamping support by using
ethtool_op_get_ts_info().
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 7939f8be d671e3e0

drivers/net/ethernet/intel/ice/ice.h

+16 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/bitmap.h>

#include <linux/log2.h>

#include <linux/ip.h>

#include <linux/sctp.h>

#include <linux/ipv6.h>

#include <linux/if_bridge.h>

#include <linux/avf/virtchnl.h>
@@ -110,6 +111,9 @@ extern const char ice_drv_ver[]; 
#define ice_for_each_alloc_rxq(vsi, i) \

	for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)



#define ice_for_each_q_vector(vsi, i) \

	for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)



struct ice_tc_info {

	u16 qoffset;

	u16 qcount_tx;
@@ -129,6 +133,17 @@ struct ice_res_tracker { 
	u16 list[1];

};



struct ice_qs_cfg {

	struct mutex *qs_mutex;  /* will be assgined to &pf->avail_q_mutex */

	unsigned long *pf_map;

	unsigned long pf_map_size;

	unsigned int q_count;

	unsigned int scatter_count;

	u16 *vsi_map;

	u16 vsi_map_offset;

	u8 mapping_mode;

};



struct ice_sw {

	struct ice_pf *pf;

	u16 sw_id;		/* switch ID for this switch */
@@ -270,6 +285,7 @@ enum ice_pf_flags { 
	ICE_FLAG_RSS_ENA,

	ICE_FLAG_SRIOV_ENA,

	ICE_FLAG_SRIOV_CAPABLE,

	ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,

	ICE_PF_FLAGS_NBITS		/* must be last */

};

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+59 −18
Original line number Diff line number Diff line
@@ -657,8 +657,13 @@ struct ice_aqc_get_topo { 


/* Update TSE (indirect 0x0403)

 * Get TSE (indirect 0x0404)

 * Add TSE (indirect 0x0401)

 * Delete TSE (indirect 0x040F)

 * Move TSE (indirect 0x0408)

 * Suspend Nodes (indirect 0x0409)

 * Resume Nodes (indirect 0x040A)

 */

struct ice_aqc_get_cfg_elem {

struct ice_aqc_sched_elem_cmd {

	__le16 num_elem_req;	/* Used by commands */

	__le16 num_elem_resp;	/* Used by responses */

	__le32 reserved;
@@ -674,18 +679,6 @@ struct ice_aqc_suspend_resume_elem { 
	__le32 teid[1];

};



/* Add TSE (indirect 0x0401)

 * Delete TSE (indirect 0x040F)

 * Move TSE (indirect 0x0408)

 */

struct ice_aqc_add_move_delete_elem {

	__le16 num_grps_req;

	__le16 num_grps_updated;

	__le32 reserved;

	__le32 addr_high;

	__le32 addr_low;

};



struct ice_aqc_elem_info_bw {

	__le16 bw_profile_idx;

	__le16 bw_alloc;
@@ -854,11 +847,46 @@ struct ice_aqc_get_phy_caps { 
#define ICE_PHY_TYPE_LOW_40GBASE_KR4		BIT_ULL(33)

#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC	BIT_ULL(34)

#define ICE_PHY_TYPE_LOW_40G_XLAUI		BIT_ULL(35)

#define ICE_PHY_TYPE_LOW_50GBASE_CR2		BIT_ULL(36)

#define ICE_PHY_TYPE_LOW_50GBASE_SR2		BIT_ULL(37)

#define ICE_PHY_TYPE_LOW_50GBASE_LR2		BIT_ULL(38)

#define ICE_PHY_TYPE_LOW_50GBASE_KR2		BIT_ULL(39)

#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC	BIT_ULL(40)

#define ICE_PHY_TYPE_LOW_50G_LAUI2		BIT_ULL(41)

#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC	BIT_ULL(42)

#define ICE_PHY_TYPE_LOW_50G_AUI2		BIT_ULL(43)

#define ICE_PHY_TYPE_LOW_50GBASE_CP		BIT_ULL(44)

#define ICE_PHY_TYPE_LOW_50GBASE_SR		BIT_ULL(45)

#define ICE_PHY_TYPE_LOW_50GBASE_FR		BIT_ULL(46)

#define ICE_PHY_TYPE_LOW_50GBASE_LR		BIT_ULL(47)

#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4	BIT_ULL(48)

#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC	BIT_ULL(49)

#define ICE_PHY_TYPE_LOW_50G_AUI1		BIT_ULL(50)

#define ICE_PHY_TYPE_LOW_100GBASE_CR4		BIT_ULL(51)

#define ICE_PHY_TYPE_LOW_100GBASE_SR4		BIT_ULL(52)

#define ICE_PHY_TYPE_LOW_100GBASE_LR4		BIT_ULL(53)

#define ICE_PHY_TYPE_LOW_100GBASE_KR4		BIT_ULL(54)

#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC	BIT_ULL(55)

#define ICE_PHY_TYPE_LOW_100G_CAUI4		BIT_ULL(56)

#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC	BIT_ULL(57)

#define ICE_PHY_TYPE_LOW_100G_AUI4		BIT_ULL(58)

#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4	BIT_ULL(59)

#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4	BIT_ULL(60)

#define ICE_PHY_TYPE_LOW_100GBASE_CP2		BIT_ULL(61)

#define ICE_PHY_TYPE_LOW_100GBASE_SR2		BIT_ULL(62)

#define ICE_PHY_TYPE_LOW_100GBASE_DR		BIT_ULL(63)

#define ICE_PHY_TYPE_LOW_MAX_INDEX		63

/* The second set of defines is for phy_type_high. */

#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4	BIT_ULL(0)

#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC	BIT_ULL(1)

#define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)

#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)

#define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)

#define ICE_PHY_TYPE_HIGH_MAX_INDEX		19



struct ice_aqc_get_phy_caps_data {

	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

	__le64 reserved;

	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */

	u8 caps;

#define ICE_AQC_PHY_EN_TX_LINK_PAUSE			BIT(0)

#define ICE_AQC_PHY_EN_RX_LINK_PAUSE			BIT(1)
@@ -923,7 +951,7 @@ struct ice_aqc_set_phy_cfg { 
/* Set PHY config command data structure */

struct ice_aqc_set_phy_cfg_data {

	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

	__le64 rsvd0;

	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */

	u8 caps;

#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY		BIT(0)

#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY		BIT(1)
@@ -1032,10 +1060,12 @@ struct ice_aqc_get_link_status_data { 
#define ICE_AQ_LINK_SPEED_20GB		BIT(6)

#define ICE_AQ_LINK_SPEED_25GB		BIT(7)

#define ICE_AQ_LINK_SPEED_40GB		BIT(8)

#define ICE_AQ_LINK_SPEED_50GB		BIT(9)

#define ICE_AQ_LINK_SPEED_100GB		BIT(10)

#define ICE_AQ_LINK_SPEED_UNKNOWN	BIT(15)

	__le32 reserved3; /* Aligns next field to 8-byte boundary */

	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

	__le64 reserved4;

	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */

};



/* Set event mask command (direct 0x0613) */
@@ -1055,6 +1085,16 @@ struct ice_aqc_set_event_mask { 
	u8	reserved1[6];

};



/* Set Port Identification LED (direct, 0x06E9) */

struct ice_aqc_set_port_id_led {

	u8 lport_num;

	u8 lport_num_valid;

	u8 ident_mode;

#define ICE_AQC_PORT_IDENT_LED_BLINK	BIT(0)

#define ICE_AQC_PORT_IDENT_LED_ORIG	0

	u8 rsvd[13];

};



/* NVM Read command (indirect 0x0701)

 * NVM Erase commands (direct 0x0702)

 * NVM Update commands (indirect 0x0703)
@@ -1341,12 +1381,12 @@ struct ice_aq_desc { 
		struct ice_aqc_get_phy_caps get_phy;

		struct ice_aqc_set_phy_cfg set_phy;

		struct ice_aqc_restart_an restart_an;

		struct ice_aqc_set_port_id_led set_port_id_led;

		struct ice_aqc_get_sw_cfg get_sw_conf;

		struct ice_aqc_sw_rules sw_rules;

		struct ice_aqc_get_topo get_topo;

		struct ice_aqc_get_cfg_elem get_update_elem;

		struct ice_aqc_sched_elem_cmd sched_elem_cmd;

		struct ice_aqc_query_txsched_res query_sched_res;

		struct ice_aqc_add_move_delete_elem add_move_delete_elem;

		struct ice_aqc_nvm nvm;

		struct ice_aqc_pf_vf_msg virt;

		struct ice_aqc_get_set_rss_lut get_set_rss_lut;
@@ -1442,6 +1482,7 @@ enum ice_adminq_opc { 
	ice_aqc_opc_restart_an				= 0x0605,

	ice_aqc_opc_get_link_status			= 0x0607,

	ice_aqc_opc_set_event_mask			= 0x0613,

	ice_aqc_opc_set_port_id_led			= 0x06E9,



	/* NVM commands */

	ice_aqc_opc_nvm_read				= 0x0701,

drivers/net/ethernet/intel/ice/ice_common.c

+146 −14
Original line number Diff line number Diff line
@@ -165,8 +165,10 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 
	cmd->param0 |= cpu_to_le16(report_mode);

	status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);



	if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP)

	if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) {

		pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);

		pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);

	}



	return status;

}
@@ -183,6 +185,9 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 
		return ICE_MEDIA_UNKNOWN;



	hw_link_info = &pi->phy.link_info;

	if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)

		/* If more than one media type is selected, report unknown */

		return ICE_MEDIA_UNKNOWN;



	if (hw_link_info->phy_type_low) {

		switch (hw_link_info->phy_type_low) {
@@ -196,6 +201,15 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 
		case ICE_PHY_TYPE_LOW_25G_AUI_C2C:

		case ICE_PHY_TYPE_LOW_40GBASE_SR4:

		case ICE_PHY_TYPE_LOW_40GBASE_LR4:

		case ICE_PHY_TYPE_LOW_50GBASE_SR2:

		case ICE_PHY_TYPE_LOW_50GBASE_LR2:

		case ICE_PHY_TYPE_LOW_50GBASE_SR:

		case ICE_PHY_TYPE_LOW_50GBASE_FR:

		case ICE_PHY_TYPE_LOW_50GBASE_LR:

		case ICE_PHY_TYPE_LOW_100GBASE_SR4:

		case ICE_PHY_TYPE_LOW_100GBASE_LR4:

		case ICE_PHY_TYPE_LOW_100GBASE_SR2:

		case ICE_PHY_TYPE_LOW_100GBASE_DR:

			return ICE_MEDIA_FIBER;

		case ICE_PHY_TYPE_LOW_100BASE_TX:

		case ICE_PHY_TYPE_LOW_1000BASE_T:
@@ -209,6 +223,11 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 
		case ICE_PHY_TYPE_LOW_25GBASE_CR_S:

		case ICE_PHY_TYPE_LOW_25GBASE_CR1:

		case ICE_PHY_TYPE_LOW_40GBASE_CR4:

		case ICE_PHY_TYPE_LOW_50GBASE_CR2:

		case ICE_PHY_TYPE_LOW_50GBASE_CP:

		case ICE_PHY_TYPE_LOW_100GBASE_CR4:

		case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:

		case ICE_PHY_TYPE_LOW_100GBASE_CP2:

			return ICE_MEDIA_DA;

		case ICE_PHY_TYPE_LOW_1000BASE_KX:

		case ICE_PHY_TYPE_LOW_2500BASE_KX:
@@ -219,10 +238,18 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 
		case ICE_PHY_TYPE_LOW_25GBASE_KR1:

		case ICE_PHY_TYPE_LOW_25GBASE_KR_S:

		case ICE_PHY_TYPE_LOW_40GBASE_KR4:

		case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:

		case ICE_PHY_TYPE_LOW_50GBASE_KR2:

		case ICE_PHY_TYPE_LOW_100GBASE_KR4:

		case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:

			return ICE_MEDIA_BACKPLANE;

		}

	} else {

		switch (hw_link_info->phy_type_high) {

		case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:

			return ICE_MEDIA_BACKPLANE;

		}

	}



	return ICE_MEDIA_UNKNOWN;

}
@@ -274,6 +301,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 
	/* update current link status information */

	hw_link_info->link_speed = le16_to_cpu(link_data.link_speed);

	hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low);

	hw_link_info->phy_type_high = le64_to_cpu(link_data.phy_type_high);

	*hw_media_type = ice_get_media_type(pi);

	hw_link_info->link_info = link_data.link_info;

	hw_link_info->an_info = link_data.an_info;
@@ -750,6 +778,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw) 
		status = ICE_ERR_CFG;

		goto err_unroll_sched;

	}

	INIT_LIST_HEAD(&hw->agg_list);



	status = ice_init_fltr_mgmt_struct(hw);

	if (status)
@@ -800,6 +829,7 @@ void ice_deinit_hw(struct ice_hw *hw) 
	ice_cleanup_fltr_mgmt_struct(hw);



	ice_sched_cleanup_all(hw);

	ice_sched_clear_agg(hw);



	if (hw->port_info) {

		devm_kfree(ice_hw_to_dev(hw), hw->port_info);
@@ -1655,7 +1685,7 @@ enum ice_status ice_get_caps(struct ice_hw *hw) 
 * This function is used to write MAC address to the NVM (0x0108).

 */

enum ice_status

ice_aq_manage_mac_write(struct ice_hw *hw, u8 *mac_addr, u8 flags,

ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,

			struct ice_sq_cd *cd)

{

	struct ice_aqc_manage_mac_write *cmd;
@@ -1667,8 +1697,8 @@ ice_aq_manage_mac_write(struct ice_hw *hw, u8 *mac_addr, u8 flags, 
	cmd->flags = flags;



	/* Prep values for flags, sah, sal */

	cmd->sah = htons(*((u16 *)mac_addr));

	cmd->sal = htonl(*((u32 *)(mac_addr + 2)));

	cmd->sah = htons(*((const u16 *)mac_addr));

	cmd->sal = htonl(*((const u32 *)(mac_addr + 2)));



	return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);

}
@@ -1705,16 +1735,20 @@ void ice_clear_pxe_mode(struct ice_hw *hw) 
/**

 * ice_get_link_speed_based_on_phy_type - returns link speed

 * @phy_type_low: lower part of phy_type

 * @phy_type_high: higher part of phy_type

 *

 * This helper function will convert a phy_type_low to its corresponding link

 * This helper function will convert an entry in phy type structure

 * [phy_type_low, phy_type_high] to its corresponding link speed.

 * Note: In the structure of [phy_type_low, phy_type_high], there should

 * be one bit set, as this function will convert one phy type to its

 * speed.

 * Note: In the structure of phy_type_low, there should be one bit set, as

 * this function will convert one phy type to its speed.

 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned

 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned

 */

static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low)

static u16

ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)

{

	u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;

	u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;



	switch (phy_type_low) {
@@ -1768,41 +1802,110 @@ static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low) 
	case ICE_PHY_TYPE_LOW_40G_XLAUI:

		speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;

		break;

	case ICE_PHY_TYPE_LOW_50GBASE_CR2:

	case ICE_PHY_TYPE_LOW_50GBASE_SR2:

	case ICE_PHY_TYPE_LOW_50GBASE_LR2:

	case ICE_PHY_TYPE_LOW_50GBASE_KR2:

	case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:

	case ICE_PHY_TYPE_LOW_50G_LAUI2:

	case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:

	case ICE_PHY_TYPE_LOW_50G_AUI2:

	case ICE_PHY_TYPE_LOW_50GBASE_CP:

	case ICE_PHY_TYPE_LOW_50GBASE_SR:

	case ICE_PHY_TYPE_LOW_50GBASE_FR:

	case ICE_PHY_TYPE_LOW_50GBASE_LR:

	case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:

	case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:

	case ICE_PHY_TYPE_LOW_50G_AUI1:

		speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;

		break;

	case ICE_PHY_TYPE_LOW_100GBASE_CR4:

	case ICE_PHY_TYPE_LOW_100GBASE_SR4:

	case ICE_PHY_TYPE_LOW_100GBASE_LR4:

	case ICE_PHY_TYPE_LOW_100GBASE_KR4:

	case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:

	case ICE_PHY_TYPE_LOW_100G_CAUI4:

	case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:

	case ICE_PHY_TYPE_LOW_100G_AUI4:

	case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:

	case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:

	case ICE_PHY_TYPE_LOW_100GBASE_CP2:

	case ICE_PHY_TYPE_LOW_100GBASE_SR2:

	case ICE_PHY_TYPE_LOW_100GBASE_DR:

		speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;

		break;

	default:

		speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;

		break;

	}



	switch (phy_type_high) {

	case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:

	case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:

	case ICE_PHY_TYPE_HIGH_100G_CAUI2:

	case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:

	case ICE_PHY_TYPE_HIGH_100G_AUI2:

		speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;

		break;

	default:

		speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;

		break;

	}



	if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&

	    speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)

		return ICE_AQ_LINK_SPEED_UNKNOWN;

	else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&

		 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)

		return ICE_AQ_LINK_SPEED_UNKNOWN;

	else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&

		 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)

		return speed_phy_type_low;

	else

		return speed_phy_type_high;

}



/**

 * ice_update_phy_type

 * @phy_type_low: pointer to the lower part of phy_type

 * @phy_type_high: pointer to the higher part of phy_type

 * @link_speeds_bitmap: targeted link speeds bitmap

 *

 * Note: For the link_speeds_bitmap structure, you can check it at

 * [ice_aqc_get_link_status->link_speed]. Caller can pass in

 * link_speeds_bitmap include multiple speeds.

 *

 * The value of phy_type_low will present a certain link speed. This helper

 * function will turn on bits in the phy_type_low based on the value of

 * Each entry in this [phy_type_low, phy_type_high] structure will

 * present a certain link speed. This helper function will turn on bits

 * in [phy_type_low, phy_type_high] structure based on the value of

 * link_speeds_bitmap input parameter.

 */

void ice_update_phy_type(u64 *phy_type_low, u16 link_speeds_bitmap)

void

ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,

		    u16 link_speeds_bitmap)

{

	u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;

	u64 pt_high;

	u64 pt_low;

	int index;



	/* We first check with low part of phy_type */

	for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {

		pt_low = BIT_ULL(index);

		speed = ice_get_link_speed_based_on_phy_type(pt_low);

		speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);



		if (link_speeds_bitmap & speed)

			*phy_type_low |= BIT_ULL(index);

	}



	/* We then check with high part of phy_type */

	for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {

		pt_high = BIT_ULL(index);

		speed = ice_get_link_speed_based_on_phy_type(0, pt_high);



		if (link_speeds_bitmap & speed)

			*phy_type_high |= BIT_ULL(index);

	}

}



/**
@@ -1934,6 +2037,7 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 
		if (ena_auto_link_update)

			cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;

		/* Copy over all the old settings */

		cfg.phy_type_high = pcaps->phy_type_high;

		cfg.phy_type_low = pcaps->phy_type_low;

		cfg.low_power_ctrl = pcaps->low_power_ctrl;

		cfg.eee_cap = pcaps->eee_cap;
@@ -2031,6 +2135,34 @@ ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 
	return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);

}



/**

 * ice_aq_set_port_id_led

 * @pi: pointer to the port information

 * @is_orig_mode: is this LED set to original mode (by the net-list)

 * @cd: pointer to command details structure or NULL

 *

 * Set LED value for the given port (0x06e9)

 */

enum ice_status

ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,

		       struct ice_sq_cd *cd)

{

	struct ice_aqc_set_port_id_led *cmd;

	struct ice_hw *hw = pi->hw;

	struct ice_aq_desc desc;



	cmd = &desc.params.set_port_id_led;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);



	if (is_orig_mode)

		cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;

	else

		cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;



	return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);

}



/**

 * __ice_aq_get_set_rss_lut

 * @hw: pointer to the hardware structure

drivers/net/ethernet/intel/ice/ice_common.h

+9 −2
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 
		enum ice_aq_res_access_type access, u32 timeout);

void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);

enum ice_status ice_init_nvm(struct ice_hw *hw);

enum ice_status ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words,

				u16 *data);

enum ice_status

ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,

		struct ice_aq_desc *desc, void *buf, u16 buf_size,
@@ -70,9 +72,10 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 
		    struct ice_aqc_get_phy_caps_data *caps,

		    struct ice_sq_cd *cd);

void

ice_update_phy_type(u64 *phy_type_low, u16 link_speeds_bitmap);

ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,

		    u16 link_speeds_bitmap);

enum ice_status

ice_aq_manage_mac_write(struct ice_hw *hw, u8 *mac_addr, u8 flags,

ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,

			struct ice_sq_cd *cd);

enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);

enum ice_status
@@ -86,6 +89,10 @@ enum ice_status 
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,

			   struct ice_sq_cd *cd);

enum ice_status

ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,

		       struct ice_sq_cd *cd);



enum ice_status

ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,

		u32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,

		struct ice_sq_cd *cmd_details);

drivers/net/ethernet/intel/ice/ice_ethtool.c

+670 −10

File changed.

Preview size limit exceeded, changes collapsed.

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