Commit 9d5fd37e authored Feb 06, 2020 by Matt Roper

drm/i915/ehl: Update port clock voltage level requirements



Voltage level depends not only on the cdclk, but also on the DDI clock.
Last time the bspec voltage level table for EHL was updated, we only
updated the cdclk requirements, but forgot to account for the new port
clock criteria.

Bspec: 21809
Fixes: d1474838 ("drm/i915/ehl: Update voltage level checks")
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200207001417.1229251-1-matthew.d.roper@intel.com


Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

parent ceaaf530

drivers/gpu/drm/i915/display/intel_ddi.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -4238,7 +4238,9 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
		void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
		struct intel_crtc_state *crtc_state)
		{
		if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
		if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
		crtc_state->min_voltage_level = 3;
		else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
		crtc_state->min_voltage_level = 1;
		else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
		crtc_state->min_voltage_level = 2;

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