Commit 9d43bade authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 APIC updates from Ingo Molnar:
 "Continued fallout of the conversion of the x86 IRQ code to the
  hierarchical irqdomain framework: more cleanups, simplifications,
  memory allocation behavior enhancements, mainly in the interrupt
  remapping and APIC code"

* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
  x86, init: Fix UP boot regression on x86_64
  iommu/amd: Fix irq remapping detection logic
  x86/acpi: Make acpi_[un]register_gsi_ioapic() depend on CONFIG_X86_LOCAL_APIC
  x86: Consolidate boot cpu timer setup
  x86/apic: Reuse apic_bsp_setup() for UP APIC setup
  x86/smpboot: Sanitize uniprocessor init
  x86/smpboot: Move apic init code to apic.c
  init: Get rid of x86isms
  x86/apic: Move apic_init_uniprocessor code
  x86/smpboot: Cleanup ioapic handling
  x86/apic: Sanitize ioapic handling
  x86/ioapic: Add proper checks to setp/enable_IO_APIC()
  x86/ioapic: Provide stub functions for IOAPIC%3Dn
  x86/smpboot: Move smpboot inlines to code
  x86/x2apic: Use state information for disable
  x86/x2apic: Split enable and setup function
  x86/x2apic: Disable x2apic from nox2apic setup
  x86/x2apic: Add proper state tracking
  x86/x2apic: Clarify remapping mode for x2apic enablement
  x86/x2apic: Move code in conditional region
  ...
parents 0ba97bc4 ba360f88

arch/x86/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -856,6 +856,10 @@ config SCHED_MC 


source "kernel/Kconfig.preempt"



config UP_LATE_INIT

       def_bool y

       depends on !SMP && X86_LOCAL_APIC



config X86_UP_APIC

	bool "Local APIC support on uniprocessors"

	depends on X86_32 && !SMP && !X86_32_NON_STANDARD

arch/x86/include/asm/apic.h

+20 −38
Original line number Diff line number Diff line
@@ -106,7 +106,14 @@ extern u32 native_safe_apic_wait_icr_idle(void); 
extern void native_apic_icr_write(u32 low, u32 id);

extern u64 native_apic_icr_read(void);



extern int x2apic_mode;

static inline bool apic_is_x2apic_enabled(void)

{

	u64 msr;



	if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))

		return false;

	return msr & X2APIC_ENABLE;

}



#ifdef CONFIG_X86_X2APIC

/*
@@ -169,48 +176,23 @@ static inline u64 native_x2apic_icr_read(void) 
	return val;

}



extern int x2apic_mode;

extern int x2apic_phys;

extern int x2apic_preenabled;

extern void check_x2apic(void);

extern void enable_x2apic(void);

extern void __init check_x2apic(void);

extern void x2apic_setup(void);

static inline int x2apic_enabled(void)

{

	u64 msr;



	if (!cpu_has_x2apic)

		return 0;



	rdmsrl(MSR_IA32_APICBASE, msr);

	if (msr & X2APIC_ENABLE)

		return 1;

	return 0;

	return cpu_has_x2apic && apic_is_x2apic_enabled();

}



#define x2apic_supported()	(cpu_has_x2apic)

static inline void x2apic_force_phys(void)

{

	x2apic_phys = 1;

}

#else

static inline void disable_x2apic(void)

{

}

static inline void check_x2apic(void)

{

}

static inline void enable_x2apic(void)

{

}

static inline int x2apic_enabled(void)

{

	return 0;

}

static inline void x2apic_force_phys(void)

{

}

static inline void check_x2apic(void) { }

static inline void x2apic_setup(void) { }

static inline int x2apic_enabled(void) { return 0; }



#define	x2apic_preenabled 0

#define	x2apic_supported()	0

#define x2apic_mode		(0)

#define	x2apic_supported()	(0)

#endif



extern void enable_IR_x2apic(void);
@@ -219,7 +201,6 @@ extern int get_physical_broadcast(void); 


extern int lapic_get_maxlvt(void);

extern void clear_local_APIC(void);

extern void connect_bsp_APIC(void);

extern void disconnect_bsp_APIC(int virt_wire_setup);

extern void disable_local_APIC(void);

extern void lapic_shutdown(void);
@@ -227,8 +208,6 @@ extern int verify_local_APIC(void); 
extern void sync_Arb_IDs(void);

extern void init_bsp_APIC(void);

extern void setup_local_APIC(void);

extern void end_local_APIC_setup(void);

extern void bsp_end_local_APIC_setup(void);

extern void init_apic_mappings(void);

void register_lapic_address(unsigned long address);

extern void setup_boot_APIC_clock(void);
@@ -236,6 +215,9 @@ extern void setup_secondary_APIC_clock(void); 
extern int APIC_init_uniprocessor(void);

extern int apic_force_enable(unsigned long addr);



extern int apic_bsp_setup(bool upmode);

extern void apic_ap_setup(void);



/*

 * On 32bit this is mach-xxx local

 */

arch/x86/include/asm/io_apic.h

+5 −0
Original line number Diff line number Diff line
@@ -279,6 +279,11 @@ static inline void disable_ioapic_support(void) { } 
#define native_ioapic_set_affinity	NULL

#define native_setup_ioapic_entry	NULL

#define native_eoi_ioapic_pin		NULL



static inline void setup_IO_APIC(void) { }

static inline void enable_IO_APIC(void) { }

static inline void setup_ioapic_dest(void) { }



#endif



#endif /* _ASM_X86_IO_APIC_H */

arch/x86/include/asm/irq_remapping.h

+0 −4
Original line number Diff line number Diff line
@@ -33,8 +33,6 @@ struct irq_cfg; 


#ifdef CONFIG_IRQ_REMAP



extern void setup_irq_remapping_ops(void);

extern int irq_remapping_supported(void);

extern void set_irq_remapping_broken(void);

extern int irq_remapping_prepare(void);

extern int irq_remapping_enable(void);
@@ -60,8 +58,6 @@ void irq_remap_modify_chip_defaults(struct irq_chip *chip); 


#else  /* CONFIG_IRQ_REMAP */



static inline void setup_irq_remapping_ops(void) { }

static inline int irq_remapping_supported(void) { return 0; }

static inline void set_irq_remapping_broken(void) { }

static inline int irq_remapping_prepare(void) { return -ENODEV; }

static inline int irq_remapping_enable(void) { return -ENODEV; }

arch/x86/include/asm/smpboot_hooks.h

deleted100644 → 0
+0 −68
Original line number Diff line number Diff line 
/* two abstractions specific to kernel/smpboot.c, mainly to cater to visws

 * which needs to alter them. */



static inline void smpboot_clear_io_apic_irqs(void)

{

#ifdef CONFIG_X86_IO_APIC

	io_apic_irqs = 0;

#endif

}



static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)

{

	unsigned long flags;



	spin_lock_irqsave(&rtc_lock, flags);

	CMOS_WRITE(0xa, 0xf);

	spin_unlock_irqrestore(&rtc_lock, flags);

	local_flush_tlb();

	pr_debug("1.\n");

	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =

							start_eip >> 4;

	pr_debug("2.\n");

	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =

							start_eip & 0xf;

	pr_debug("3.\n");

}



static inline void smpboot_restore_warm_reset_vector(void)

{

	unsigned long flags;



	/*

	 * Install writable page 0 entry to set BIOS data area.

	 */

	local_flush_tlb();



	/*

	 * Paranoid:  Set warm reset code and vector here back

	 * to default values.

	 */

	spin_lock_irqsave(&rtc_lock, flags);

	CMOS_WRITE(0, 0xf);

	spin_unlock_irqrestore(&rtc_lock, flags);



	*((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;

}



static inline void __init smpboot_setup_io_apic(void)

{

#ifdef CONFIG_X86_IO_APIC

	/*

	 * Here we can be sure that there is an IO-APIC in the system. Let's

	 * go and set it up:

	 */

	if (!skip_ioapic_setup && nr_ioapics)

		setup_IO_APIC();

	else {

		nr_ioapics = 0;

	}

#endif

}



static inline void smpboot_clear_io_apic(void)

{

#ifdef CONFIG_X86_IO_APIC

	nr_ioapics = 0;

#endif

}

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