Commit 9d265124 authored by Daniel Yeisley's avatar Daniel Yeisley Committed by Greg Kroah-Hartman
Browse files

[PATCH] PCI Quirk: 1K I/O space granularity on Intel P64H2 



I've implemented a quirk to take advantage of the 1KB I/O space
granularity option on the Intel P64H2 PCI Bridge.  I had to change
probe.c because it sets the resource start and end to be aligned on 4k
boundaries (after the quirk sets them to 1k boundaries).  I've tested
this patch on a Unisys ES7000-600 both with and without the 1KB option
enabled.  I also tested this on a 2 processor Dell box that doesn't have
a P64H2 to make sure there were no negative affects there.

Signed-off-by: default avatarDan Yeisley <dan.yeisley@unisys.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 81f15442

drivers/pci/probe.c

+4 −2
Original line number Diff line number Diff line
@@ -264,7 +264,9 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child) 


	if (base <= limit) {

		res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;

		if (!res->start)

			res->start = base;

		if (!res->end)

			res->end = limit + 0xfff;

	}

drivers/pci/quirks.c

+26 −0
Original line number Diff line number Diff line
@@ -1342,6 +1342,32 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 
	pci_do_fixups(dev, start, end);

}



/* Enable 1k I/O space granularity on the Intel P64H2 */

static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)

{

	u16 en1k;

	u8 io_base_lo, io_limit_lo;

	unsigned long base, limit;

	struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;



	pci_read_config_word(dev, 0x40, &en1k);



	if (en1k & 0x200) {

		printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");



		pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);

		pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);

		base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;

		limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;



		if (base <= limit) {

			res->start = base;

			res->end = limit + 0x3ff;

		}

	}

}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	0x1460,		quirk_p64h2_1k_io);



EXPORT_SYMBOL(pcie_mch_quirk);

#ifdef CONFIG_HOTPLUG

EXPORT_SYMBOL(pci_fixup_device);

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