spi: tegra114: add 3 wire transfer mode support (9d199231) · Commits · 戴 / test

This patch adds 3 wire transfer support to SPI mode list along with its implementation. 3 wire or Bi-directional mode uses only one serial data pin for the transfer. SPI in master mode uses MOSI data line only and MISO data line is not used. Signed-off-by:

Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by:

Mark Brown <broonie@kernel.org>

drivers/spi/spi-tegra114.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -754,6 +754,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
		else
		command1 &= ~SPI_LSBIT_FE;

		if (spi->mode & SPI_3WIRE)
		command1 \|= SPI_BIDIROE;
		else
		command1 &= ~SPI_BIDIROE;

		if (tspi->cs_control) {
		if (tspi->cs_control != spi)
		tegra_spi_writel(tspi, command1, SPI_COMMAND1);
		@@ -1158,7 +1163,7 @@ static int tegra_spi_probe(struct platform_device *pdev)

		/* the spi->mode bits understood by this driver: */
		master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LSB_FIRST \|
		SPI_TX_DUAL \| SPI_RX_DUAL;
		SPI_TX_DUAL \| SPI_RX_DUAL \| SPI_3WIRE;
		master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
		master->setup = tegra_spi_setup;
		master->transfer_one_message = tegra_spi_transfer_one_message;

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